Module cc13x2_cc26x2_pac::aux_sysif::clkshiftdet

Clock Shift Detection A transition in the MCU domain state causes a non-accumulative change to the SCE clock period when the AUX clock rate is derived from SCLK_MF or SCLK_LF: - A single SCE clock cycle is 6 thru 8 SCLK_HF cycles longer when MCU domain enters active state. - A single SCE clock cycle is 6 thru 8 SCLK_HF cycles shorter when MCU domain exits active state. AUX_SCE detects if such events occurred to the SCE clock during the time period between a clear of STAT and a read of STAT.

Structs

R	Value read from the register
RESERVED1R	Value of the field
STATR	Value of the field
W	Value to write to the register
_RESERVED1W	Proxy
_STATW	Proxy