cc13x2_cc26x2_pac/i2c0/
smis.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::SMIS {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct RESERVED3R {
47    bits: u32,
48}
49impl RESERVED3R {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bits(&self) -> u32 {
53        self.bits
54    }
55}
56#[doc = r" Value of the field"]
57pub struct STOPMISR {
58    bits: bool,
59}
60impl STOPMISR {
61    #[doc = r" Value of the field as raw bits"]
62    #[inline]
63    pub fn bit(&self) -> bool {
64        self.bits
65    }
66    #[doc = r" Returns `true` if the bit is clear (0)"]
67    #[inline]
68    pub fn bit_is_clear(&self) -> bool {
69        !self.bit()
70    }
71    #[doc = r" Returns `true` if the bit is set (1)"]
72    #[inline]
73    pub fn bit_is_set(&self) -> bool {
74        self.bit()
75    }
76}
77#[doc = r" Value of the field"]
78pub struct STARTMISR {
79    bits: bool,
80}
81impl STARTMISR {
82    #[doc = r" Value of the field as raw bits"]
83    #[inline]
84    pub fn bit(&self) -> bool {
85        self.bits
86    }
87    #[doc = r" Returns `true` if the bit is clear (0)"]
88    #[inline]
89    pub fn bit_is_clear(&self) -> bool {
90        !self.bit()
91    }
92    #[doc = r" Returns `true` if the bit is set (1)"]
93    #[inline]
94    pub fn bit_is_set(&self) -> bool {
95        self.bit()
96    }
97}
98#[doc = r" Value of the field"]
99pub struct DATAMISR {
100    bits: bool,
101}
102impl DATAMISR {
103    #[doc = r" Value of the field as raw bits"]
104    #[inline]
105    pub fn bit(&self) -> bool {
106        self.bits
107    }
108    #[doc = r" Returns `true` if the bit is clear (0)"]
109    #[inline]
110    pub fn bit_is_clear(&self) -> bool {
111        !self.bit()
112    }
113    #[doc = r" Returns `true` if the bit is set (1)"]
114    #[inline]
115    pub fn bit_is_set(&self) -> bool {
116        self.bit()
117    }
118}
119#[doc = r" Proxy"]
120pub struct _RESERVED3W<'a> {
121    w: &'a mut W,
122}
123impl<'a> _RESERVED3W<'a> {
124    #[doc = r" Writes raw bits to the field"]
125    #[inline]
126    pub unsafe fn bits(self, value: u32) -> &'a mut W {
127        const MASK: u32 = 536870911;
128        const OFFSET: u8 = 3;
129        self.w.bits &= !((MASK as u32) << OFFSET);
130        self.w.bits |= ((value & MASK) as u32) << OFFSET;
131        self.w
132    }
133}
134#[doc = r" Proxy"]
135pub struct _STOPMISW<'a> {
136    w: &'a mut W,
137}
138impl<'a> _STOPMISW<'a> {
139    #[doc = r" Sets the field bit"]
140    pub fn set_bit(self) -> &'a mut W {
141        self.bit(true)
142    }
143    #[doc = r" Clears the field bit"]
144    pub fn clear_bit(self) -> &'a mut W {
145        self.bit(false)
146    }
147    #[doc = r" Writes raw bits to the field"]
148    #[inline]
149    pub fn bit(self, value: bool) -> &'a mut W {
150        const MASK: bool = true;
151        const OFFSET: u8 = 2;
152        self.w.bits &= !((MASK as u32) << OFFSET);
153        self.w.bits |= ((value & MASK) as u32) << OFFSET;
154        self.w
155    }
156}
157#[doc = r" Proxy"]
158pub struct _STARTMISW<'a> {
159    w: &'a mut W,
160}
161impl<'a> _STARTMISW<'a> {
162    #[doc = r" Sets the field bit"]
163    pub fn set_bit(self) -> &'a mut W {
164        self.bit(true)
165    }
166    #[doc = r" Clears the field bit"]
167    pub fn clear_bit(self) -> &'a mut W {
168        self.bit(false)
169    }
170    #[doc = r" Writes raw bits to the field"]
171    #[inline]
172    pub fn bit(self, value: bool) -> &'a mut W {
173        const MASK: bool = true;
174        const OFFSET: u8 = 1;
175        self.w.bits &= !((MASK as u32) << OFFSET);
176        self.w.bits |= ((value & MASK) as u32) << OFFSET;
177        self.w
178    }
179}
180#[doc = r" Proxy"]
181pub struct _DATAMISW<'a> {
182    w: &'a mut W,
183}
184impl<'a> _DATAMISW<'a> {
185    #[doc = r" Sets the field bit"]
186    pub fn set_bit(self) -> &'a mut W {
187        self.bit(true)
188    }
189    #[doc = r" Clears the field bit"]
190    pub fn clear_bit(self) -> &'a mut W {
191        self.bit(false)
192    }
193    #[doc = r" Writes raw bits to the field"]
194    #[inline]
195    pub fn bit(self, value: bool) -> &'a mut W {
196        const MASK: bool = true;
197        const OFFSET: u8 = 0;
198        self.w.bits &= !((MASK as u32) << OFFSET);
199        self.w.bits |= ((value & MASK) as u32) << OFFSET;
200        self.w
201    }
202}
203impl R {
204    #[doc = r" Value of the register as raw bits"]
205    #[inline]
206    pub fn bits(&self) -> u32 {
207        self.bits
208    }
209    #[doc = "Bits 3:31 - 31:3\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
210    #[inline]
211    pub fn reserved3(&self) -> RESERVED3R {
212        let bits = {
213            const MASK: u32 = 536870911;
214            const OFFSET: u8 = 3;
215            ((self.bits >> OFFSET) & MASK as u32) as u32
216        };
217        RESERVED3R { bits }
218    }
219    #[doc = "Bit 2 - 2:2\\] Stop condition masked interrupt status 0: An interrupt has not occurred or is masked/disabled. 1: An unmasked Stop condition interrupt is pending. This bit is cleared by writing a 1 to the SICR.STOPIC."]
220    #[inline]
221    pub fn stopmis(&self) -> STOPMISR {
222        let bits = {
223            const MASK: bool = true;
224            const OFFSET: u8 = 2;
225            ((self.bits >> OFFSET) & MASK as u32) != 0
226        };
227        STOPMISR { bits }
228    }
229    #[doc = "Bit 1 - 1:1\\] Start condition masked interrupt status 0: An interrupt has not occurred or is masked/disabled. 1: An unmasked Start condition interrupt is pending. This bit is cleared by writing a 1 to the SICR.STARTIC."]
230    #[inline]
231    pub fn startmis(&self) -> STARTMISR {
232        let bits = {
233            const MASK: bool = true;
234            const OFFSET: u8 = 1;
235            ((self.bits >> OFFSET) & MASK as u32) != 0
236        };
237        STARTMISR { bits }
238    }
239    #[doc = "Bit 0 - 0:0\\] Data masked interrupt status 0: An interrupt has not occurred or is masked/disabled. 1: An unmasked data received or data requested interrupt is pending. This bit is cleared by writing a 1 to the SICR.DATAIC."]
240    #[inline]
241    pub fn datamis(&self) -> DATAMISR {
242        let bits = {
243            const MASK: bool = true;
244            const OFFSET: u8 = 0;
245            ((self.bits >> OFFSET) & MASK as u32) != 0
246        };
247        DATAMISR { bits }
248    }
249}
250impl W {
251    #[doc = r" Reset value of the register"]
252    #[inline]
253    pub fn reset_value() -> W {
254        W { bits: 0 }
255    }
256    #[doc = r" Writes raw bits to the register"]
257    #[inline]
258    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
259        self.bits = bits;
260        self
261    }
262    #[doc = "Bits 3:31 - 31:3\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
263    #[inline]
264    pub fn reserved3(&mut self) -> _RESERVED3W {
265        _RESERVED3W { w: self }
266    }
267    #[doc = "Bit 2 - 2:2\\] Stop condition masked interrupt status 0: An interrupt has not occurred or is masked/disabled. 1: An unmasked Stop condition interrupt is pending. This bit is cleared by writing a 1 to the SICR.STOPIC."]
268    #[inline]
269    pub fn stopmis(&mut self) -> _STOPMISW {
270        _STOPMISW { w: self }
271    }
272    #[doc = "Bit 1 - 1:1\\] Start condition masked interrupt status 0: An interrupt has not occurred or is masked/disabled. 1: An unmasked Start condition interrupt is pending. This bit is cleared by writing a 1 to the SICR.STARTIC."]
273    #[inline]
274    pub fn startmis(&mut self) -> _STARTMISW {
275        _STARTMISW { w: self }
276    }
277    #[doc = "Bit 0 - 0:0\\] Data masked interrupt status 0: An interrupt has not occurred or is masked/disabled. 1: An unmasked data received or data requested interrupt is pending. This bit is cleared by writing a 1 to the SICR.DATAIC."]
278    #[inline]
279    pub fn datamis(&mut self) -> _DATAMISW {
280        _DATAMISW { w: self }
281    }
282}
cc13x2_cc26x2_pac/i2c0/smis.rs

cc13x2_cc26x2_pac/i2c0/
smis.rs
