[−][src]Module cc13x2_cc26x2_pac::aux_timer2
AUX Timer2 (AUX_TIMER2) offers flexible: - generation of waveforms and events. - capture of signal period and duty cycle. - generation of single clock pulse. It consists of a: - 16-bit counter. - 4 capture compare channels. - 4 event outputs, which are mapped to AUX event bus, see EVCTL. Each channel subscribes to the asynchronous AUX event bus. They can control one or more event outputs in both capture and compare modes. AUX_SYSIF:TIMER2CLKCTL.SRC selects clock source for the timer.
Modules
| ch0cc | Channel 0 Capture Compare |
| ch0pcc | Channel 0 Pipeline Capture Compare |
| ch0ccfg | Channel 0 Capture Configuration |
| ch0evcfg | Channel 0 Event Configuration This register configures channel function and enables event outputs. Each channel has an edge-detection circuit with memory. The circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode. The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. |
| ch1evcfg | Channel 1 Event Configuration This register configures channel function and enables event outputs. Each channel has an edge-detection circuit with memory. The circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode. The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. |
| ch1ccfg | Channel 1 Capture Configuration |
| ch1pcc | Channel 1 Pipeline Capture Compare |
| ch1cc | Channel 1 Capture Compare |
| ch2evcfg | Channel 2 Event Configuration This register configures channel function and enables event outputs. Each channel has an edge-detection circuit with memory. The circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode. The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. |
| ch2ccfg | Channel 2 Capture Configuration |
| ch2pcc | Channel 2 Pipeline Capture Compare |
| ch2cc | Channel 2 Capture Compare |
| ch3evcfg | Channel 3 Event Configuration This register configures channel function and enables event outputs. Each channel has an edge-detection circuit with memory. The circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode. The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. |
| ch3ccfg | Channel 3 Capture Configuration |
| ch3pcc | Channel 3 Pipeline Capture Compare |
| ch3cc | Channel 3 Capture Compare |
| cntr | Counter |
| ctl | Timer Control |
| evctl | Event Control Set and clear individual events manually. Manual update of an event takes priority over automatic channel updates to the same event. You cannot set and clear an event at the same time, such requests will be neglected. An event can be automatically cleared, set, toggled, or pulsed by each channel, listed in decreasing order of priority. The action with highest priority happens when multiple channels want to update an event at the same time. The four events connect to the asynchronous AUX event bus: - Event 0 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. - Event 1 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. - Event 2 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. - Event 3 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. |
| precfg | Clock Prescaler Configuration |
| pulsetrig | Pulse Trigger |
| shdwtarget | Shadow Target |
| target | Target User defined counter target. |
Structs
| CH0CC | Channel 0 Capture Compare |
| CH0PCC | Channel 0 Pipeline Capture Compare |
| CH0CCFG | Channel 0 Capture Configuration |
| CH0EVCFG | Channel 0 Event Configuration This register configures channel function and enables event outputs. Each channel has an edge-detection circuit with memory. The circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode. The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. |
| CH1EVCFG | Channel 1 Event Configuration This register configures channel function and enables event outputs. Each channel has an edge-detection circuit with memory. The circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode. The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. |
| CH1CCFG | Channel 1 Capture Configuration |
| CH1PCC | Channel 1 Pipeline Capture Compare |
| CH1CC | Channel 1 Capture Compare |
| CH2EVCFG | Channel 2 Event Configuration This register configures channel function and enables event outputs. Each channel has an edge-detection circuit with memory. The circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode. The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. |
| CH2CCFG | Channel 2 Capture Configuration |
| CH2PCC | Channel 2 Pipeline Capture Compare |
| CH2CC | Channel 2 Capture Compare |
| CH3EVCFG | Channel 3 Event Configuration This register configures channel function and enables event outputs. Each channel has an edge-detection circuit with memory. The circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode. The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. |
| CH3CCFG | Channel 3 Capture Configuration |
| CH3PCC | Channel 3 Pipeline Capture Compare |
| CH3CC | Channel 3 Capture Compare |
| CNTR | Counter |
| CTL | Timer Control |
| EVCTL | Event Control Set and clear individual events manually. Manual update of an event takes priority over automatic channel updates to the same event. You cannot set and clear an event at the same time, such requests will be neglected. An event can be automatically cleared, set, toggled, or pulsed by each channel, listed in decreasing order of priority. The action with highest priority happens when multiple channels want to update an event at the same time. The four events connect to the asynchronous AUX event bus: - Event 0 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. - Event 1 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. - Event 2 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. - Event 3 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. |
| PRECFG | Clock Prescaler Configuration |
| PULSETRIG | Pulse Trigger |
| RegisterBlock | Register block |
| SHDWTARGET | Shadow Target |
| TARGET | Target User defined counter target. |