Module cc13x2_cc26x2_pac::i2c0

I2CMaster/Slave Serial Controler

Modules

mcr	Master Configuration This register configures the mode (Master or Slave) and sets the interface for test mode loopback.
mctrl	Master Control This register accesses status bits when read and control bits when written. When read, the status register indicates the state of the I2C bus controller as stated in MSTAT. When written, the control register configures the I2C controller operation. To generate a single transmit cycle, the I2C Master Slave Address (MSA) register is written with the desired address, the MSA.RS bit is cleared, and this register is written with * ACK=X (0 or 1), * STOP=1, * START=1, * RUN=1 to perform the operation and stop. When the operation is completed (or aborted due an error), an interrupt becomes active and the data may be read from the MDR register.
mdr	Master Data This register contains the data to be transmitted when in the Master Transmit state and the data received when in the Master Receive state.
micr	Master Interrupt Clear This register clears the raw and masked interrupt.
mimr	Master Interrupt Mask This register controls whether a raw interrupt is promoted to a controller interrupt.
mmis	Master Masked Interrupt Status This register show which interrupt is active (based on result from MRIS and MIMR).
mris	Master Raw Interrupt Status This register show the unmasked interrupt status.
msa	Master Salve Address This register contains seven address bits of the slave to be accessed by the master (a6-a0), and an RS bit determining if the next operation is a receive or transmit.
mstat	Master Status
mtpr	I2C Master Timer Period This register specifies the period of the SCL clock.
sctl	Slave Control Note: This register shares address with SSTAT, meaning that this register functions as a control register when written, and a status register when read.
sdr	Slave Data This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state.
sicr	Slave Interrupt Clear This register clears the raw interrupt SRIS.
simr	Slave Interrupt Mask This register controls whether a raw interrupt is promoted to a controller interrupt.
smis	Slave Masked Interrupt Status This register show which interrupt is active (based on result from SRIS and SIMR).
soar	Slave Own Address This register consists of seven address bits that identify this I2C device on the I2C bus.
sris	Slave Raw Interrupt Status This register shows the unmasked interrupt status.
sstat	Slave Status Note: This register shares address with SCTL, meaning that this register functions as a control register when written, and a status register when read.

Structs

MCR	Master Configuration This register configures the mode (Master or Slave) and sets the interface for test mode loopback.
MCTRL	Master Control This register accesses status bits when read and control bits when written. When read, the status register indicates the state of the I2C bus controller as stated in MSTAT. When written, the control register configures the I2C controller operation. To generate a single transmit cycle, the I2C Master Slave Address (MSA) register is written with the desired address, the MSA.RS bit is cleared, and this register is written with * ACK=X (0 or 1), * STOP=1, * START=1, * RUN=1 to perform the operation and stop. When the operation is completed (or aborted due an error), an interrupt becomes active and the data may be read from the MDR register.
MDR	Master Data This register contains the data to be transmitted when in the Master Transmit state and the data received when in the Master Receive state.
MICR	Master Interrupt Clear This register clears the raw and masked interrupt.
MIMR	Master Interrupt Mask This register controls whether a raw interrupt is promoted to a controller interrupt.
MMIS	Master Masked Interrupt Status This register show which interrupt is active (based on result from MRIS and MIMR).
MRIS	Master Raw Interrupt Status This register show the unmasked interrupt status.
MSA	Master Salve Address This register contains seven address bits of the slave to be accessed by the master (a6-a0), and an RS bit determining if the next operation is a receive or transmit.
MSTAT	Master Status
MTPR	I2C Master Timer Period This register specifies the period of the SCL clock.
RegisterBlock	Register block
SCTL	Slave Control Note: This register shares address with SSTAT, meaning that this register functions as a control register when written, and a status register when read.
SDR	Slave Data This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state.
SICR	Slave Interrupt Clear This register clears the raw interrupt SRIS.
SIMR	Slave Interrupt Mask This register controls whether a raw interrupt is promoted to a controller interrupt.
SMIS	Slave Masked Interrupt Status This register show which interrupt is active (based on result from SRIS and SIMR).
SOAR	Slave Own Address This register consists of seven address bits that identify this I2C device on the I2C bus.
SRIS	Slave Raw Interrupt Status This register shows the unmasked interrupt status.
SSTAT	Slave Status Note: This register shares address with SCTL, meaning that this register functions as a control register when written, and a status register when read.