Module cc13x2_cc26x2_pac::aux_tdc

AUX Time To Digital Converter (AUX_TDC) is used to measure the time between two events with high resolution. AUX_TDC consists of a state machine that operates at AUX bus rate and an asynchronous fast-counter which is clocked by the TDC clock. DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL configures TDC clock source. The fast-counter counts on both edges of the TDC clock to double the resolution. See the Technical Reference Manual for event timing requirements.

Modules

ctl	Control
precntr	Prescaler Counter
prectl	Prescaler Control The prescaler can be used to count events that are faster than the AUX bus rate. It can be used to: - count pulses on a specified event from the asynchronous event bus. - prescale a specified event from the asynchronous event bus. To use the prescaler output as an event source in TDC measurements you must set both TRIGSRC.START_SRC and TRIGSRC.STOP_SRC to AUX_TDC_PRE. It is recommended to use the prescaler when the signal frequency to measure exceeds 1/10th of the AUX bus rate.
result	Result Result of last TDC conversion.
satcfg	Saturation Configuration
stat	Status
trigcnt	Trigger Counter Stop-counter control and status.
trigcntcfg	Trigger Counter Configuration Stop-counter configuration.
trigcntload	Trigger Counter Load Stop-counter load.
trigsrc	Trigger Source Select source and polarity for TDC start and stop events. See the Technical Reference Manual for event timing requirements.

Structs

CTL	Control
PRECNTR	Prescaler Counter
PRECTL	Prescaler Control The prescaler can be used to count events that are faster than the AUX bus rate. It can be used to: - count pulses on a specified event from the asynchronous event bus. - prescale a specified event from the asynchronous event bus. To use the prescaler output as an event source in TDC measurements you must set both TRIGSRC.START_SRC and TRIGSRC.STOP_SRC to AUX_TDC_PRE. It is recommended to use the prescaler when the signal frequency to measure exceeds 1/10th of the AUX bus rate.
RESULT	Result Result of last TDC conversion.
RegisterBlock	Register block
SATCFG	Saturation Configuration
STAT	Status
TRIGCNT	Trigger Counter Stop-counter control and status.
TRIGCNTCFG	Trigger Counter Configuration Stop-counter configuration.
TRIGCNTLOAD	Trigger Counter Load Stop-counter load.
TRIGSRC	Trigger Source Select source and polarity for TDC start and stop events. See the Technical Reference Manual for event timing requirements.