Module cc13x2_cc26x2_pac::aux_aiodio3

AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can: - be connected to analog AUX modules, such as comparators and ADC. - be used by AUX_SCE. - connect to AUX_SPIM SCLK, MISO and MOSI signals. - connect to the asynchronous AUX event bus. Enabled digital inputs are synchronized at SCE clock rate. Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO[n] does not map to DIO[n]. AUXIO-DIO remapping is handled by Sensor Controller Studio.

Modules

gpiodie	General Purpose Input Output Digital Input Enable This register controls input buffers for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
gpiodin	General Purpose Input Output Data In This register provides synchronized input data for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth
gpiodout	General Purpose Input Output Data Out The output data register is used to set data on AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
gpiodoutclr	General Purpose Input Output Data Out Clear Clear bits in GPIODOUT instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
gpiodoutset	General Purpose Input Output Data Out Set Set bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
gpiodouttgl	General Purpose Input Output Data Out Toggle Toggle bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
io0psel	Input Output 0 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is 1. To avoid glitches on AUXIO[8i+0] you must configure this register while IOPOE bit 0 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
io1psel	Input Output 1 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is 1. To avoid glitches on AUXIO[8i+1] you must configure this register while IOPOE bit 1 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
io2psel	Input Output 2 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is 1. To avoid glitches on AUXIO[8i+2] you must configure this register while IOPOE bit 2 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
io3psel	Input Output 3 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is 1. To avoid glitches on AUXIO[8i+3] you must configure this register while IOPOE bit 3 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
io4psel	Input Output 4 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is 1. To avoid glitches on AUXIO[8i+4] you must configure this register while IOPOE bit 4 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
io5psel	Input Output 5 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is 1. To avoid glitches on AUXIO[8i+5] you must configure this register while IOPOE bit 5 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
io6psel	Input Output 6 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is 1. To avoid glitches on AUXIO[8i+6] you must configure this register while IOPOE bit 6 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
io7psel	Input Output 7 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is 1. To avoid glitches on AUXIO[8i+7] you must configure this register while IOPOE bit 7 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
iomode	Input Output Mode This register controls pull-up, pull-down, and output mode for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
iomodeh	Input Output Mode High This is an alias register for IOMODE.IO4 thru IOMODE.IO7.
iomodel	Input Output Mode Low This is an alias register for IOMODE.IO0 thru IOMODE.IO3.
iopoe	Input Output Peripheral Output Enable This register selects the output source for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Structs

GPIODIE	General Purpose Input Output Digital Input Enable This register controls input buffers for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
GPIODIN	General Purpose Input Output Data In This register provides synchronized input data for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth
GPIODOUT	General Purpose Input Output Data Out The output data register is used to set data on AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
GPIODOUTCLR	General Purpose Input Output Data Out Clear Clear bits in GPIODOUT instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
GPIODOUTSET	General Purpose Input Output Data Out Set Set bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
GPIODOUTTGL	General Purpose Input Output Data Out Toggle Toggle bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
IO0PSEL	Input Output 0 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is 1. To avoid glitches on AUXIO[8i+0] you must configure this register while IOPOE bit 0 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
IO1PSEL	Input Output 1 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is 1. To avoid glitches on AUXIO[8i+1] you must configure this register while IOPOE bit 1 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
IO2PSEL	Input Output 2 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is 1. To avoid glitches on AUXIO[8i+2] you must configure this register while IOPOE bit 2 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
IO3PSEL	Input Output 3 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is 1. To avoid glitches on AUXIO[8i+3] you must configure this register while IOPOE bit 3 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
IO4PSEL	Input Output 4 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is 1. To avoid glitches on AUXIO[8i+4] you must configure this register while IOPOE bit 4 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
IO5PSEL	Input Output 5 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is 1. To avoid glitches on AUXIO[8i+5] you must configure this register while IOPOE bit 5 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
IO6PSEL	Input Output 6 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is 1. To avoid glitches on AUXIO[8i+6] you must configure this register while IOPOE bit 6 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
IO7PSEL	Input Output 7 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is 1. To avoid glitches on AUXIO[8i+7] you must configure this register while IOPOE bit 7 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
IOMODE	Input Output Mode This register controls pull-up, pull-down, and output mode for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
IOMODEH	Input Output Mode High This is an alias register for IOMODE.IO4 thru IOMODE.IO7.
IOMODEL	Input Output Mode Low This is an alias register for IOMODE.IO0 thru IOMODE.IO3.
IOPOE	Input Output Peripheral Output Enable This register selects the output source for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
RegisterBlock	Register block