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#[doc = r" Value read from the register"] pub struct R { bits: u32, } #[doc = r" Value to write to the register"] pub struct W { bits: u32, } impl super::CFG { #[doc = r" Modifies the contents of the register"] #[inline] pub fn modify<F>(&self, f: F) where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, { let bits = self.register.get(); let r = R { bits: bits }; let mut w = W { bits: bits }; f(&r, &mut w); self.register.set(w.bits); } #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { R { bits: self.register.get(), } } #[doc = r" Writes to the register"] #[inline] pub fn write<F>(&self, f: F) where F: FnOnce(&mut W) -> &mut W, { let mut w = W::reset_value(); f(&mut w); self.register.set(w.bits); } #[doc = r" Writes the reset value to the register"] #[inline] pub fn reset(&self) { self.write(|w| w) } } #[doc = r" Value of the field"] pub struct RESERVED8R { bits: u32, } impl RESERVED8R { #[doc = r" Value of the field as raw bits"] #[inline] pub fn bits(&self) -> u32 { self.bits } } #[doc = r" Value of the field"] pub struct PRTOCTRLR { bits: u8, } impl PRTOCTRLR { #[doc = r" Value of the field as raw bits"] #[inline] pub fn bits(&self) -> u8 { self.bits } } #[doc = r" Value of the field"] pub struct RESERVED1R { bits: u8, } impl RESERVED1R { #[doc = r" Value of the field as raw bits"] #[inline] pub fn bits(&self) -> u8 { self.bits } } #[doc = r" Value of the field"] pub struct MASTERENABLER { bits: bool, } impl MASTERENABLER { #[doc = r" Value of the field as raw bits"] #[inline] pub fn bit(&self) -> bool { self.bits } #[doc = r" Returns `true` if the bit is clear (0)"] #[inline] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r" Returns `true` if the bit is set (1)"] #[inline] pub fn bit_is_set(&self) -> bool { self.bit() } } #[doc = r" Proxy"] pub struct _RESERVED8W<'a> { w: &'a mut W, } impl<'a> _RESERVED8W<'a> { #[doc = r" Writes raw bits to the field"] #[inline] pub unsafe fn bits(self, value: u32) -> &'a mut W { const MASK: u32 = 16777215; const OFFSET: u8 = 8; self.w.bits &= !((MASK as u32) << OFFSET); self.w.bits |= ((value & MASK) as u32) << OFFSET; self.w } } #[doc = r" Proxy"] pub struct _PRTOCTRLW<'a> { w: &'a mut W, } impl<'a> _PRTOCTRLW<'a> { #[doc = r" Writes raw bits to the field"] #[inline] pub unsafe fn bits(self, value: u8) -> &'a mut W { const MASK: u8 = 7; const OFFSET: u8 = 5; self.w.bits &= !((MASK as u32) << OFFSET); self.w.bits |= ((value & MASK) as u32) << OFFSET; self.w } } #[doc = r" Proxy"] pub struct _RESERVED1W<'a> { w: &'a mut W, } impl<'a> _RESERVED1W<'a> { #[doc = r" Writes raw bits to the field"] #[inline] pub unsafe fn bits(self, value: u8) -> &'a mut W { const MASK: u8 = 15; const OFFSET: u8 = 1; self.w.bits &= !((MASK as u32) << OFFSET); self.w.bits |= ((value & MASK) as u32) << OFFSET; self.w } } #[doc = r" Proxy"] pub struct _MASTERENABLEW<'a> { w: &'a mut W, } impl<'a> _MASTERENABLEW<'a> { #[doc = r" Sets the field bit"] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r" Clears the field bit"] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r" Writes raw bits to the field"] #[inline] pub fn bit(self, value: bool) -> &'a mut W { const MASK: bool = true; const OFFSET: u8 = 0; self.w.bits &= !((MASK as u32) << OFFSET); self.w.bits |= ((value & MASK) as u32) << OFFSET; self.w } } impl R { #[doc = r" Value of the register as raw bits"] #[inline] pub fn bits(&self) -> u32 { self.bits } #[doc = "Bits 8:31 - 31:8\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."] #[inline] pub fn reserved8(&self) -> RESERVED8R { let bits = { const MASK: u32 = 16777215; const OFFSET: u8 = 8; ((self.bits >> OFFSET) & MASK as u32) as u32 }; RESERVED8R { bits } } #[doc = "Bits 5:7 - 7:5\\] Sets the AHB-Lite bus protocol protection state by controlling the AHB signal HProt\\[3:1\\] as follows: Bit \\[7\\] Controls HProt\\[3\\] to indicate if a cacheable access is occurring. Bit \\[6\\] Controls HProt\\[2\\] to indicate if a bufferable access is occurring. Bit \\[5\\] Controls HProt\\[1\\] to indicate if a privileged access is occurring. When bit \\[n\\] = 1 then the corresponding HProt bit is high. When bit \\[n\\] = 0 then the corresponding HProt bit is low. This field controls HProt\\[3:1\\] signal for all transactions initiated by uDMA except two transactions below: - the read from the address indicated by source address pointer - the write to the address indicated by destination address pointer HProt\\[3:1\\] for these two exceptions can be controlled by dedicated fields in the channel configutation descriptor."] #[inline] pub fn prtoctrl(&self) -> PRTOCTRLR { let bits = { const MASK: u8 = 7; const OFFSET: u8 = 5; ((self.bits >> OFFSET) & MASK as u32) as u8 }; PRTOCTRLR { bits } } #[doc = "Bits 1:4 - 4:1\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."] #[inline] pub fn reserved1(&self) -> RESERVED1R { let bits = { const MASK: u8 = 15; const OFFSET: u8 = 1; ((self.bits >> OFFSET) & MASK as u32) as u8 }; RESERVED1R { bits } } #[doc = "Bit 0 - 0:0\\] Enables the controller: 0: Disables the controller 1: Enables the controller"] #[inline] pub fn masterenable(&self) -> MASTERENABLER { let bits = { const MASK: bool = true; const OFFSET: u8 = 0; ((self.bits >> OFFSET) & MASK as u32) != 0 }; MASTERENABLER { bits } } } impl W { #[doc = r" Reset value of the register"] #[inline] pub fn reset_value() -> W { W { bits: 0 } } #[doc = r" Writes raw bits to the register"] #[inline] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; self } #[doc = "Bits 8:31 - 31:8\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."] #[inline] pub fn reserved8(&mut self) -> _RESERVED8W { _RESERVED8W { w: self } } #[doc = "Bits 5:7 - 7:5\\] Sets the AHB-Lite bus protocol protection state by controlling the AHB signal HProt\\[3:1\\] as follows: Bit \\[7\\] Controls HProt\\[3\\] to indicate if a cacheable access is occurring. Bit \\[6\\] Controls HProt\\[2\\] to indicate if a bufferable access is occurring. Bit \\[5\\] Controls HProt\\[1\\] to indicate if a privileged access is occurring. When bit \\[n\\] = 1 then the corresponding HProt bit is high. When bit \\[n\\] = 0 then the corresponding HProt bit is low. This field controls HProt\\[3:1\\] signal for all transactions initiated by uDMA except two transactions below: - the read from the address indicated by source address pointer - the write to the address indicated by destination address pointer HProt\\[3:1\\] for these two exceptions can be controlled by dedicated fields in the channel configutation descriptor."] #[inline] pub fn prtoctrl(&mut self) -> _PRTOCTRLW { _PRTOCTRLW { w: self } } #[doc = "Bits 1:4 - 4:1\\] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."] #[inline] pub fn reserved1(&mut self) -> _RESERVED1W { _RESERVED1W { w: self } } #[doc = "Bit 0 - 0:0\\] Enables the controller: 0: Disables the controller 1: Enables the controller"] #[inline] pub fn masterenable(&mut self) -> _MASTERENABLEW { _MASTERENABLEW { w: self } } }