[−][src]Module cc13x2_cc26x2_hal::aux_anaif::dacsmplctl
DAC Sample Control The DAC sample clock maintains the DAC voltage stored in the sample-and-hold capacitor. The DAC sample clock waveform consists of a setup phase followed by a hold phase. In the setup phase the sample-and-hold capacitor charges to the programmed voltage. The hold phase maintains the voltage with minimal power. DACSMPLCFG0 and DACSMPLCFG1 configure the DAC sample clock waveform.
Structs
ENR | Value of the field |
R | Value read from the register |
RESERVED7R | Value of the field |
W | Value to write to the register |
_ENW | Proxy |
_RESERVED7W | Proxy |