Module cc13x2_cc26x2_hal::aux_anaif::dacsmplcfg1

DAC Sample Configuration 1 The sample clock period equals (high time + low time) * base period. DACSMPLCFG0.CLKDIV determines the base period. Timing requirements (DAC Buffer On / DAC Buffer Off): - (high time + low time) * base period > (4 us / 1 us) - (high time * base period) > (2 us / 0.5 us) - (low time * base period) > (2 us / 0.5 us) - (low time * base period + HOLD_INTERVAL * sample clock period) < 32 us If AUX_SYSIF:OPMODEREQ.REQ equals PDLP, you must set: - H_PER = L_PER = HOLD_INTERVAL = 0.

Structs

HOLD_INTERVALR	Value of the field
H_PERR	Value of the field
L_PERR	Value of the field
R	Value read from the register
RESERVED15R	Value of the field
SETUP_CNTR	Value of the field
W	Value to write to the register
_HOLD_INTERVALW	Proxy
_H_PERW	Proxy
_L_PERW	Proxy
_RESERVED15W	Proxy
_SETUP_CNTW	Proxy