Module cc13x2_cc26x2_hal::ssi1

Synchronous Serial Interface with master and slave capabilities

Modules

cpsr	Clock Prescale
cr0	Control 0
cr1	Control 1
dmacr	DMA Control
dr	Data 16-bits wide data register: When read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When written, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.
icr	Interrupt Clear On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.
imsc	Interrupt Mask Set and Clear
mis	Masked Interrupt Status
reserved1	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
reserved2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
ris	Raw Interrupt Status
sr	Status

Structs

CPSR	Clock Prescale
CR0	Control 0
CR1	Control 1
DMACR	DMA Control
DR	Data 16-bits wide data register: When read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When written, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.
ICR	Interrupt Clear On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.
IMSC	Interrupt Mask Set and Clear
MIS	Masked Interrupt Status
RESERVED1	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
RIS	Raw Interrupt Status
RegisterBlock	Register block
SR	Status