[−][src]Module cc13x2_cc26x2_hal::i2c0::mctrl
Master Control This register accesses status bits when read and control bits when written. When read, the status register indicates the state of the I2C bus controller as stated in MSTAT. When written, the control register configures the I2C controller operation. To generate a single transmit cycle, the I2C Master Slave Address (MSA) register is written with the desired address, the MSA.RS bit is cleared, and this register is written with * ACK=X (0 or 1), * STOP=1, * START=1, * RUN=1 to perform the operation and stop. When the operation is completed (or aborted due an error), an interrupt becomes active and the data may be read from the MDR register.
Structs
| R | Value read from the register |
| RESERVED4R | Value of the field |
| W | Value to write to the register |
| _ACKW | Proxy |
| _RESERVED4W | Proxy |
| _RUNW | Proxy |
| _STARTW | Proxy |
| _STOPW | Proxy |
Enums
| ACKR | Possible values of the field |
| ACKW | Values that can be written to the field |
| RUNR | Possible values of the field |
| RUNW | Values that can be written to the field |
| STARTR | Possible values of the field |
| STARTW | Values that can be written to the field |
| STOPR | Possible values of the field |
| STOPW | Values that can be written to the field |