[−][src]Module cc13x2_cc26x2_hal::cpu_scs::ccr
Configuration Control This register is used to enable NMI, HardFault and FAULTMASK to ignore bus fault, trap divide by zero and unaligned accesses, enable user access to the Software Trigger Interrupt Register (STIR), control entry to Thread Mode.
Structs
| BFHFNMIGNR | Value of the field |
| DIV_0_TRPR | Value of the field |
| NONBASETHREDENAR | Value of the field |
| R | Value read from the register |
| RESERVED2R | Value of the field |
| RESERVED5R | Value of the field |
| RESERVED10R | Value of the field |
| STKALIGNR | Value of the field |
| UNALIGN_TRPR | Value of the field |
| USERSETMPENDR | Value of the field |
| W | Value to write to the register |
| _BFHFNMIGNW | Proxy |
| _DIV_0_TRPW | Proxy |
| _NONBASETHREDENAW | Proxy |
| _RESERVED2W | Proxy |
| _RESERVED5W | Proxy |
| _RESERVED10W | Proxy |
| _STKALIGNW | Proxy |
| _UNALIGN_TRPW | Proxy |
| _USERSETMPENDW | Proxy |