Module cc13x2_cc26x2_hal::aux_spim

The AUX Serial Peripheral Interface Master (AUX_SPIM) enables AUX_SCE with power-efficient SPI communication. It is not possible to write a register while SPI transmission occurs. An attempt to do so will stall the bus until transmission is complete. Read of RX8.DATA or RX16.DATA stalls the bus until LSB has been captured. Read of SCLKIDLE.STAT or DATAIDLE.STAT stalls the bus until condition described is met. Other read operations do not stall the bus. AUX_SCE becomes clock gated if it encounters a bus stall. This is useful as AUX_SCE can write TX8.DATA and then read RX8.DATA immediately to read a SPI slave. In such case there is no need for software to wait or to poll registers. AUX_SYSIF:PEROPRATE.SPIM_OP_RATE selects the peripheral clock frequency which is used to derive the SCLK frequency. AUX_SCE must set AUX_SYSIF:PEROPRATE.SPIM_OP_RATE to SCE_RATE to access and use AUX_SPIM. System CPU must set AUX_SYSIF:PEROPRATE.SPIM_OP_RATE to BUS_RATE to access and use AUX_SPIM. Failure to do so can result in incorrect SPI transmission.

Modules

dataidle	Data Idle Read operation stalls until current transfer completes.
misocfg	MISO Configuration Write operation stalls until current transfer completes.
mosictl	MOSI Control Write operation stalls until current transfer completes.
rx8	Receive 8 Bit Read operation stalls until current transfer completes.
rx16	Receive 16 Bit Read operation stalls until current transfer completes.
sclkidle	SCLK Idle Read operation stalls until SCLK is idle with no remaining clock edges.
spimcfg	SPI Master Configuration Write operation stalls until current transfer completes.
tx8	Transmit 8 Bit Write operation stalls until current transfer completes.
tx16	Transmit 16 Bit Write operation stalls until current transfer completes.

Structs

DATAIDLE	Data Idle Read operation stalls until current transfer completes.
MISOCFG	MISO Configuration Write operation stalls until current transfer completes.
MOSICTL	MOSI Control Write operation stalls until current transfer completes.
RX8	Receive 8 Bit Read operation stalls until current transfer completes.
RX16	Receive 16 Bit Read operation stalls until current transfer completes.
RegisterBlock	Register block
SCLKIDLE	SCLK Idle Read operation stalls until SCLK is idle with no remaining clock edges.
SPIMCFG	SPI Master Configuration Write operation stalls until current transfer completes.
TX8	Transmit 8 Bit Write operation stalls until current transfer completes.
TX16	Transmit 16 Bit Write operation stalls until current transfer completes.