Module bitvec::order

In-Element Bit Ordering

The bitvec memory model is designed to separate the semantic ordering of bits in an abstract memory space from the electrical ordering of latches in real memory. This module provides the bridge between the two domains with the BitOrder trait and implementations of it.

The BitOrder trait bridges semantic indices (marked by the BitIdx type) to electrical position counters (morked by the BitPos type) or selection masks (marked by the BitSel and BitMask types).

Because BitOrder is open for client crates to implement, this module also provides verification functions for the test suite that ensure a given BitOrder implementation is correct for all the register types that it will govern. See the verify_for_type or verify functions for more information.

Re-exports

pub use self::Lsb0 as LocalBits;

Structs

Lsb0

Least-Significant-First Bit Traversal

Msb0

Most-Significant-First Bit Traversal

Traits

BitOrder

In-Element Bit Ordering

Functions

verify

Complete BitOrder Verification

verify_for_type

Single-Type BitOrder Verification