Module bitbang_hal::spi

source ·
Expand description

Serial Peripheral Interface

This implementation consumes the following hardware resources:

  • Periodic timer to mark clock cycles
  • Output GPIO pin for clock signal (SCLK)
  • Output GPIO pin for data transmission (Master Output Slave Input - MOSI)
  • Input GPIO pin for data reception (Master Input Slave Output - MISO)

The timer must be configured to twice the desired communication frequency.

SS/CS (slave select) must be handled independently.

MSB-first and LSB-first bit orders are supported.

Structs§

  • SPI
    A Full-Duplex SPI implementation, takes 3 pins, and a timer running at 2x the desired SPI frequency.

Enums§

Constants§

  • MODE_0
    Helper for CPOL = 0, CPHA = 0
  • MODE_1
    Helper for CPOL = 0, CPHA = 1
  • MODE_2
    Helper for CPOL = 1, CPHA = 0
  • MODE_3
    Helper for CPOL = 1, CPHA = 1