| bus_errors0 | Bits 0-7 of CTRL_BUS_ERRORS.
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| bus_errors1 | Bits 8-15 of CTRL_BUS_ERRORS.
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| bus_errors2 | Bits 16-23 of CTRL_BUS_ERRORS.
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| bus_errors3 | Bits 24-31 of CTRL_BUS_ERRORS. Total number of Wishbone bus errors (timeouts) since last reset.
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| reset | Write a 1 to this register to reset the SoC.
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| scratch0 | Bits 0-7 of CTRL_SCRATCH.
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| scratch1 | Bits 8-15 of CTRL_SCRATCH.
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| scratch2 | Bits 16-23 of CTRL_SCRATCH.
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| scratch3 | Bits 24-31 of CTRL_SCRATCH. Use this register as a scratch space to verify that software read/write accesses to the Wishbone/CSR bus are working correctly. The initial reset value of 0x1234578 can be used to verify endianness.
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| BUS_ERRORS0 | Bits 0-7 of CTRL_BUS_ERRORS.
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| BUS_ERRORS1 | Bits 8-15 of CTRL_BUS_ERRORS.
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| BUS_ERRORS2 | Bits 16-23 of CTRL_BUS_ERRORS.
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| BUS_ERRORS3 | Bits 24-31 of CTRL_BUS_ERRORS. Total number of Wishbone bus errors (timeouts) since last reset.
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| RESET | Write a 1 to this register to reset the SoC.
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| SCRATCH0 | Bits 0-7 of CTRL_SCRATCH.
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| SCRATCH1 | Bits 8-15 of CTRL_SCRATCH.
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| SCRATCH2 | Bits 16-23 of CTRL_SCRATCH.
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| SCRATCH3 | Bits 24-31 of CTRL_SCRATCH. Use this register as a scratch space to verify that software read/write accesses to the Wishbone/CSR bus are working correctly. The initial reset value of 0x1234578 can be used to verify endianness.
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