//! rust-bcm-2709-spi
//!
//! Low-performance SPI interface to BCM2709 hardware peripherals via mmap(...) and direct memory I/O.
//! 
//! For use when you don't/can't load a specific driver on Raspberry Pi.  It is probably better
//! to use SPIDev kernel module. But this may help for some testing in a pinch.
//! 
//! Usage
//! -----
//! ```
//! extern crate bcm2709_spi;
//! use bcm2709_spi::{gpio, spi, DirectMemory};
//! 
//! pub fn main() {
//!   let mem = match DirectMemory::get() {
//!     Err(x) => { println!("Failed: {}", x); return; },
//!     Ok(x) => x
//!   }
//!   
//!   let spi = match mem.spi() {
//!     Err(x) => { println!("Couldn't create SPI: {}", x); return; },
//!     Ok(x)  => x
//!   }
//!   
//!   spi.set_clock( 32 );   // Recommend above 4; loopback misses bits at clk=4.
//!   
//!   spi.start_transaction();
//!   let byte_read = spi.write_byte( b'A' );   // =65u8 when a loopback wire placed between MISO and MOSI
//!   spi.stop_transaction();
//! }
//!

extern crate libc;
extern crate vcell;



/// Linux has 4KB size pages.  Offsets in `mmap()` should align to MAP_BLOCK_SIZE.
const MAP_BLOCK_SIZE: usize = 4 * 1024;

const SPI_BASE_OFFSET: usize = 0x3f20_4000;
const GPIO_BASE_OFFSET: usize = 0x3f20_0000;


// SPI will be initialized to single-byte operation: each Read/Write to FIFO will dequeue/enqueue
// one byte into the FIFO (LSB).
//
#[doc = "SPI hardware implementation; borrowed from constructs from Japaric's SVD2Rust MCU rust-code generator"]
pub mod spi {
    use vcell::VolatileCell;
    use super::{ libc, SPI_BASE_OFFSET, MAP_BLOCK_SIZE };

    pub struct SPIInterface {
        #[doc = r"bit-1: CPOL, bit-0: CPHA;  SPI mode for the device"]
        pub mode: u8,
        #[doc = r"RaspberryPi has 2 chip select lines for this SPI device. Set this to the device number to drive"]
        pub device: u8,

        address: usize,
    }

    #[repr(C)]
    pub struct SPI {
        cs: CS,
        #[doc = r"FIFO buffer; read/write to this to get SPI data"]
        fifo: FIFO,
        #[doc = r"CLK divisor; generates SPI clock from core clock. Must be a power of 2. Rounds down to lowest power of 2. 0 = divide-by 65536"]
        clk: CLK,
    }

    impl SPIInterface {
        pub fn new(fd: i32) -> Self {
            let ptr;
            unsafe {
                ptr = libc::mmap( 0 as *mut libc::c_void, 
                                  MAP_BLOCK_SIZE, 
                                  libc::PROT_READ | libc::PROT_WRITE,
                                  libc::MAP_SHARED,
                                  fd,
                                  SPI_BASE_OFFSET as libc::off_t);
            }
            return SPIInterface { 
                mode: 0,
                device: 0,
                address: ptr as usize, 
            };
        }

        pub fn get<'a>(&'a mut self) -> &'a mut SPI {
            let ptr: *mut SPI = self.address as *mut SPI;
            unsafe{ return &mut *ptr; }
        }

        pub fn set_clock(&mut self, clk: u16) {
            let spi = self.get();
            spi.clk.register.set(clk as u32);
        }


        #[inline(always)]
        pub fn start_transaction(&mut self) {
            let device = self.device;
            let mode = self.mode;

            let spi = self.get();
            let bits = cs::CLEAR_RX_FIFO | cs::CLEAR_TX_FIFO | cs::TA | 
                ((( mode & 0x3) as u32) << 2) | 
                (( device & 0x3) as u32);
            spi.cs.register.set( bits );
        }


        #[inline(always)]
        pub fn stop_transaction(&mut self) {
            let spi = self.get();
            
            // Clear out any pending data
            spi.cs.wait_for_done();        

            let bits = spi.cs.register.get() & !cs::TA;
            spi.cs.register.set(bits);
        }

        #[inline(always)]
        pub fn write_byte(&mut self, byte: u8) -> u8 {
            let spi = self.get();

            // Clear out any pending data
            spi.cs.wait_for_done();        

            spi.fifo.register.set( byte as u32 );

            // Clear out any pending data
            spi.cs.wait_for_done();        

            return (spi.fifo.register.get() & 0xFF) as u8;;
        }
    }
    
    impl Drop for SPIInterface {
        fn drop(&mut self) {
            unsafe {
                libc::munmap( self.address as *mut libc::c_void, MAP_BLOCK_SIZE as libc::size_t );
            }
        }
    }


    pub struct CS {
        register: VolatileCell<u32>,
    }

    pub mod cs {
        pub const RXF: u32 = (1 << 20);
        pub const RXR: u32 = (1 << 19);
        pub const TXD: u32 = (1 << 18);
        pub const RXD: u32 = (1 << 17);
        pub const DONE: u32 = (1 << 16);
        pub const TA: u32  = (1 << 7);
        pub const CLEAR_RX_FIFO: u32 = (1 << 5);
        pub const CLEAR_TX_FIFO: u32 = (1 << 4);
        pub const CPOL: u32 = (1 << 3);
        pub const CPHA: u32 = (1 << 2);

        #[doc = r"Value read from the register"]
        pub struct R {
            bits: u32,
        }
        #[doc = r"Value to write to the register"]
        pub struct W {
            bits: u32,
        }
        impl super::CS {
            #[doc = r"Modifies the content of the CS register"]
            #[inline(always)]
            pub fn modify<F>(&self, f: F)
            where
                for<'w> F: FnOnce(&R, &'w W) -> &'w mut W,
            {
                let bits = self.register.get();
                let r = R { bits: bits };
                let mut w = W { bits: bits };
                f(&r, &mut w);
                self.register.set(w.bits);
            }
            #[doc = r"Reads the contents of the CS register"]
            #[inline(always)]
            pub fn read(&self) -> R {
                R { bits: self.register.get() }
            }
            #[doc = r"Writes to the register"]
            #[inline(always)]
            pub fn write<F>(&self, f: F)
            where
                F: FnOnce(&mut W) -> &mut W,
            {
                let mut w = W::reset_value();
                f(&mut w);
                self.register.set(w.bits);
            }
            #[doc = r"Writes reset value to the register"]
            #[inline(always)]
            pub fn reset(&self) {
                self.write(|w| w)
            }


            #[doc = r"Waits for the DONE bit to be set; will wait indefinitely"]
            #[inline(always)]
            pub fn wait_for_done(&self) {
                while (self.register.get() & DONE) == 0 {
                }
            }

        }
        #[doc = r"value of the field"]
        pub struct CSR {
            bits: u32,
        }
        impl CSR {
            #[doc = r"Value of the field as raw bits"]
            #[inline(always)]
            pub fn bits(&self) -> u32 {
                self.bits
            }
        }
        #[doc = r"Proxy"]
        pub struct _CSW<'a> {
            w: &'a mut W,
        }
        impl<'a> _CSW<'a> {
            #[doc = r"Writes raw bits to the field"]
            #[inline(always)]
            pub unsafe fn bits(self, value:u32) -> &'a mut W {
                const MASK: u32 = 0xFFFF_FFFF;
                const OFFSET: u8 = 0;
                self.w.bits &= !((MASK as u32) << OFFSET);
                self.w.bits |= ((value & MASK) as u32) << OFFSET;
                self.w
            }
        }
        impl R {
            #[doc = r"Value of the register as raw bits"]
            #[inline(always)]
            pub fn bits(&self) -> u32 {
                self.bits
            }
            #[doc = "Bits 0:31 - Control status register bits"]
            #[inline(always)]
            pub fn csr(&self) -> CSR {
                let bits = {
                    const MASK: u32 = 0xFFFF_FFFF;
                    const OFFSET: u8 = 0;
                    ((self.bits >> OFFSET) & MASK as u32) as u32
                };
                CSR { bits }
            }
        }

        impl W {
            #[doc = r"Reset value of the register"]
            #[inline(always)]
            pub fn reset_value() -> W {
                W { bits: (1 << 12) as u32 }
            }
            #[doc = r"Write raw bits to the register"]
            #[inline(always)]
            pub fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
            #[doc = r"Bits 0:31 - Control status register bits"]
            #[inline(always)]
            pub fn cs(&mut self) -> _CSW {
                _CSW { w: self }
            }
        }
    }

    pub struct FIFO {
        register: VolatileCell<u32>,
    }
    pub mod fifo {
        #[doc = r"Value read from the register"]
        pub struct R {
            bits: u32,
        }
        #[doc = r"Value to write to the register"]
        pub struct W {
            bits: u32,
        }

        impl super::FIFO {
            #[doc = r"Modifies the content of the FIFO register"]
            #[inline(always)]
            pub fn modify<F>(&self, f: F)
            where
                for<'w> F: FnOnce(&R, &'w W) -> &'w mut W,
            {
                let bits = self.register.get();
                let r = R { bits: bits };
                let mut w = W { bits: bits };
                f(&r, &mut w);
                self.register.set(w.bits);
            }
            #[doc = r"Reads the contents of the FIFO register"]
            #[inline(always)]
            pub fn read(&self) -> R {
                R { bits: self.register.get() }
            }
            #[doc = r"Writes to the register"]
            #[inline(always)]
            pub fn write<F>(&self, f: F)
            where
                F: FnOnce(&mut W) -> &mut W,
            {
                let mut w = W::reset_value();
                f(&mut w);
                self.register.set(w.bits);
            }
            #[doc = r"Writes reset value to the register"]
            #[inline(always)]
            pub fn reset(&self) {
                self.write(|w| w)
            }

        }
        #[doc = r"value of the field"]
        pub struct FIFOR {
            bits: u32,
        }
        impl FIFOR {
            #[doc = r"Value of the field as raw bits"]
            #[inline(always)]
            pub fn bits(&self) -> u32 {
                self.bits
            }
        }
        #[doc = r"Proxy"]
        pub struct _FIFOW<'a> {
            w: &'a mut W,
        }
        impl<'a> _FIFOW<'a> {
            #[doc = r"Writes raw bits to the field"]
            #[inline(always)]
            pub unsafe fn bits(self, value:u32) -> &'a mut W {
                const MASK: u32 = 0xFFFF_FFFF;
                const OFFSET: u8 = 0;
                self.w.bits &= !((MASK as u32) << OFFSET);
                self.w.bits |= ((value & MASK) as u32) << OFFSET;
                self.w
            }
        }
        impl R {
            #[doc = r"Value of the register as raw bits"]
            #[inline(always)]
            pub fn bits(&self) -> u32 {
                self.bits
            }
            #[doc = "Bits 0:31 - Control status register bits"]
            #[inline(always)]
            pub fn fifor(&self) -> FIFOR  {
                let bits = {
                    const MASK: u32 = 0xFFFF_FFFF;
                    const OFFSET: u8 = 0;
                    ((self.bits >> OFFSET) & MASK as u32) as u32
                };
                FIFOR { bits }
            }
        }
        impl W {
            #[doc = r"Reset value of the register"]
            #[inline(always)]
            pub fn reset_value() -> W {
                W { bits: 0 as u32 }
            }
            #[doc = r"Write raw bits to the register"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
            #[doc = r"Bits 0:31 - Control status register bits"]
            #[inline(always)]
            pub fn fifo(&mut self) -> _FIFOW {
                _FIFOW { w: self }
            }
        }
    }

    pub struct CLK {
        register: VolatileCell<u32>,
    }
    pub mod clk {
        #[doc = r"Value read from the register"]
        pub struct R {
            bits: u32,
        }
        #[doc = r"Value to write to the register"]
        pub struct W {
            bits: u32,
        }

        impl super::CLK {
            #[doc = r"Modifies the content of the FIFO register"]
            #[inline(always)]
            pub fn modify<F>(&self, f: F)
            where
                for<'w> F: FnOnce(&R, &'w W) -> &'w mut W,
            {
                let bits = self.register.get();
                let r = R { bits: bits };
                let mut w = W { bits: bits };
                f(&r, &mut w);
                self.register.set(w.bits);
            }
            #[doc = r"Reads the contents of the FIFO register"]
            #[inline(always)]
            pub fn read(&self) -> R {
                R { bits: self.register.get() }
            }
            #[doc = r"Writes to the register"]
            #[inline(always)]
            pub fn write<F>(&self, f: F)
            where
                F: FnOnce(&mut W) -> &mut W,
            {
                let mut w = W::reset_value();
                f(&mut w);
                self.register.set(w.bits);
            }
            #[doc = r"Writes reset value to the register"]
            #[inline(always)]
            pub fn reset(&self) {
                self.write(|w| w)
            }

        }

        #[doc = r"value of the field"]
        pub struct CLKR {
            bits: u32,
        }
        impl CLKR {
            #[doc = r"Value of the field as raw bits"]
            #[inline(always)]
            pub fn bits(&self) -> u32 {
                self.bits
            }
        }
        #[doc = r"Proxy"]
        pub struct _CLKW<'a> {
            w: &'a mut W,
        }
        impl<'a> _CLKW<'a> {
            #[doc = r"Writes raw bits to the field"]
            #[inline(always)]
            pub unsafe fn bits(self, value:u32) -> &'a mut W {
                const MASK: u32 = 0x0000_FFFF;
                const OFFSET: u8 = 0;
                self.w.bits &= !((MASK as u32) << OFFSET);
                self.w.bits |= ((value & MASK) as u32) << OFFSET;
                self.w
            }
        }
        impl R {
            #[doc = r"Value of the register as raw bits"]
            #[inline(always)]
            pub fn bits(&self) -> u32 {
                self.bits
            }
            #[doc = "Bits 0:31 - Control status register bits"]
            #[inline(always)]
            pub fn clkr(&self) -> CLKR  {
                let bits = {
                    const MASK: u32 = 0x0000_FFFF;
                    const OFFSET: u8 = 0;
                    ((self.bits >> OFFSET) & MASK as u32) as u32
                };
                CLKR { bits }
            }
        }
        impl W {
            #[doc = r"Reset value of the register"]
            #[inline(always)]
            pub fn reset_value() -> W {
                W { bits: 0 as u32 }
            }
            #[doc = r"Write raw bits to the register"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
            #[doc = r"Bits 0:31 - Control status register bits"]
            #[inline(always)]
            pub fn clk(&mut self) -> _CLKW {
                _CLKW { w: self }
            }
        }
    }
}


#[doc = r"Interface for getting structs to map to /dev/mem blocks"]
pub struct DirectMemory {
    fd: i32,
}

/// 
/// Lifetimes and mmap(...) access:
/// -------------------------------
///
/// On file descriptor close, memory is not unmapped.  From POSIX, the memory mapped from a file
/// can continue to be used until it is unmapped, even if the file is closed before the unmap.
///
/// This means that the GPIO and SPI (mmapped access) to _/dev/mem_ can remain active and call
/// **munmap(...)** when Dropped, which will fully close out the resource.
///
///
impl DirectMemory {
    #[doc = r"Opens /dev/mem; may not succeed."]
    pub fn get() -> Result<Self, &'static str> {
        let fd;
        unsafe {
            fd = libc::open( "/dev/mem".as_ptr() as *const u8, libc::O_RDWR | libc::O_SYNC | libc::O_CLOEXEC );
        }
        if fd < 0 {
            return Err("Could not open /dev/mem");
        }

        Ok( DirectMemory { 
            fd: fd, 
            } )
    }

    #[doc = r"Creates the GPIO interface"]
    pub fn gpio(&mut self) -> Result<gpio::GPIOInterface, &'static str> {
        return Ok(gpio::GPIOInterface::new( self.fd ) );
    }

    #[doc = r"Creates the SPI interface; takes ownership via GPIO of all SPI pins: SPI_CE1, SPI_CE0, SPI_MISO, SPI_MOSI, SPI_CLK"]
    pub fn spi(&mut self) -> Result<spi::SPIInterface, &'static str> {
        let mut gpio_per = self.gpio()?;
        gpio_per.fsel( 7, gpio::FSEL_0 );  // SPI_CE1
        gpio_per.fsel( 8, gpio::FSEL_0 );  // SPI_CE0
        gpio_per.fsel( 9, gpio::FSEL_0 );  // SPI_MISO
        gpio_per.fsel(10, gpio::FSEL_0 );  // SPI_MOSI
        gpio_per.fsel(11, gpio::FSEL_0 );  // SPI_CLK

        return Ok(spi::SPIInterface::new(self.fd));
    }
}

impl Drop for DirectMemory {
    #[doc = r"Close the /dev/mem file descriptor on drop"]
    fn drop(&mut self) {
        if self.fd == 0 {
            return;
        }
        unsafe {
            libc::close( self.fd );
        }
    }
}



#[doc = r"Simplified GPIO interface; reads/writes to direct memory. Take care not to conflict with /sys/class/gpio interface."]
pub mod gpio {
    use vcell::VolatileCell;
    use super::{libc, MAP_BLOCK_SIZE, GPIO_BASE_OFFSET};

    pub const FSEL_INPUT: u8 = 0;
    pub const FSEL_OUTPUT: u8 = 1;
    pub const FSEL_0: u8 = 0b100;
    pub const FSEL_1: u8 = 0b101;
    pub const FSEL_2: u8 = 0b110;
    pub const FSEL_3: u8 = 0b111;
    pub const FSEL_4: u8 = 0b011;
    pub const FSEL_5: u8 = 0b010;

    #[doc = r"User-accessible interface to GPIO"]
    pub struct GPIOInterface {
        address: usize,
    }

    impl GPIOInterface {

        pub fn get<'b>(&'b mut self) -> &'b mut GPIO {
            let ptr: *mut GPIO = self.address as *mut GPIO;
            unsafe { return &mut *ptr; }
        }

        pub fn new(fd: i32) -> Self {
            unsafe {
                let ptr = libc::mmap( 0 as *mut libc::c_void, 
                                      MAP_BLOCK_SIZE, 
                                      libc::PROT_READ | libc::PROT_WRITE, 
                                      libc::MAP_SHARED, 
                                      fd, 
                                      GPIO_BASE_OFFSET as libc::off_t);
                return GPIOInterface { 
                    address: ptr as usize, 
                };
            }
        }

        #[doc = r"Sets the pin function"]
        #[inline(always)]
        pub fn fsel(&mut self, pin: usize, mode: u8 ) {
            let gpio = self.get();

            let bank = pin / 10 as usize;
            let mut val =  gpio.gpfsel[bank].get() ;
            let shift = (pin - (10 * bank) ) * 3;
            let mask = !((0x07 << shift) as u32);
            val = (val & mask) | ((mode as u32) << shift);
            gpio.gpfsel[bank].set(val);
        }

        #[doc = r"Sets an output pin to HIGH"]
        #[inline(always)]
        pub fn pin_high( &mut self, pin: usize ) {
            let gpio = self.get();

            let bank = pin / 32 as usize;
            let shift = pin - (32 * bank) ;
            let val = 1 << shift;
            gpio.gpset[bank].set(val);
        }
        #[doc = r"Sets an output pin to LOW"]
        #[inline(always)]
        pub fn pin_low(&mut self, pin: usize) {
            let gpio = self.get();

            let bank = pin / 32 as usize;
            let shift = pin - (32 * bank) ;
            let val = 1 << shift;
            gpio.gpclr[bank].set(val);
        }

    }
    impl Drop for GPIOInterface {
        #[doc = r"Unmaps the GPIO peripheral block memory with munmap(...)"]
        fn drop(&mut self) {
            unsafe {
                libc::munmap( self.address as *mut libc::c_void, MAP_BLOCK_SIZE as libc::size_t );
            }
        }
    }


    #[doc = r"GPIO peripheral structure, allows direct memory access to peripheral registers"]
    #[repr(C)]
    pub struct GPIO {
        gpfsel: [VolatileCell<u32>; 6],
        res0: u32,
        gpset: [VolatileCell<u32>; 2],
        res1: u32,
        gpclr: [VolatileCell<u32>; 2],

    }

    impl GPIO {


    }
}



#[cfg(test)]
mod tests {

    use super::{DirectMemory, gpio };

    #[test]
    #[allow(dead_code)]
    #[allow(unused_variables)]
    fn smoke_direct_memory() {
        let mem = match DirectMemory::get() {
            Ok(mem) => mem,
            Err(reason) => {
                println!("somke_direct_memory(): error: {}", reason);
                return;
            }
        };
        println!("smoke_direct_memory: success.");
    }

    #[test]
    #[allow(dead_code)]
    #[allow(unused_variables)]
    fn test_gpio_create() {
        let mut mem = DirectMemory::get().unwrap();
        let gpio = mem.gpio();
    }

    #[test]
    fn test_gpio_fsel_out() {
        let mut mem = DirectMemory::get().unwrap();
        let mut gpio_iface = mem.gpio().unwrap();
        gpio_iface.fsel( 26, gpio::FSEL_OUTPUT );
    }
    #[test]
    fn test_gpio_fsel_in() {
        let mut mem = DirectMemory::get().unwrap();
        let mut gpio_iface = mem.gpio().unwrap();
        gpio_iface.fsel( 26, gpio::FSEL_INPUT );
    }
    #[test]
    fn test_gpio_set_low() {
        let mut mem = DirectMemory::get().unwrap();
        let mut gpio_iface = mem.gpio().unwrap();
        gpio_iface.pin_low( 26 );
    }
    #[test]
    fn test_gpio_set_high() {
        let mut mem = DirectMemory::get().unwrap();
        let mut gpio_iface = mem.gpio().unwrap();
        gpio_iface.pin_high( 26 );
    }

    #[test]
    #[allow(dead_code)]
    fn test_spi_init() {
        let mut mem = DirectMemory::get().unwrap();
        #[allow(unused_variables)]
        let spi_iface = mem.spi();

    }

    #[test]
    fn test_spi_write() {
        println!("test_spi_write()");
        let mut mem = DirectMemory::get().unwrap();
        let mut spi_iface = mem.spi().unwrap();
        spi_iface.set_clock(32);
        spi_iface.start_transaction();
        spi_iface.write_byte( b'A' );
        spi_iface.stop_transaction();
        println!("done");
    }
}