//! The AVR ATxmega32A4U microcontroller
//!
//! # Variants
//! |        | Pinout | Mcuage | Operating temperature | Operating voltage | Max speed |
//! |--------|--------|---------|-----------------------|-------------------|-----------|
//! | ATxmega32A4U-AU | QFP-QFN-44 | TQFP44 | -40°C - 85°C | 1.6V - 3.6V | 32 MHz |
//! | ATxmega32A4U-MH | QFP-QFN-44 | VQFN44 | -40°C - 85°C | 1.6V - 3.6V | 32 MHz |
//! | ATxmega32A4U-CU | BGA-49 | VFBGA49 | -40°C - 85°C | 1.6V - 3.6V | 32 MHz |
//! | ATxmega32A4U-AN | QFP-QFN-44 | TQFP44 | -40°C - 105°C | 1.6V - 3.6V | 32 MHz |
//! | ATxmega32A4U-M7 | QFP-QFN-44 | VQFN44 | -40°C - 105°C | 1.6V - 3.6V | 32 MHz |
//!

#![allow(non_upper_case_globals)]

/// General Power Reduction.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | EVSYS | 10 |
/// | RTC | 100 |
/// | DMA | 1 |
/// | USB | 1000000 |
/// | AES | 10000 |
pub const PRGEN: *mut u8 = 0x0 as *mut u8;

/// Control Register.
pub const CTRL: *mut u8 = 0x0 as *mut u8;

/// RCOSC 2 MHz Calibration Value B.
pub const RCOSC2M: *mut u8 = 0x0 as *mut u8;

/// Multi-pin Configuration Mask.
pub const MPCMASK: *mut u8 = 0x0 as *mut u8;

/// I/O Port Data Direction.
pub const DIR: *mut u8 = 0x0 as *mut u8;

/// Address Register 0.
pub const ADDR0: *mut u8 = 0x0 as *mut u8;

/// General Purpose IO Register 0.
pub const GPIOR0: *mut u8 = 0x0 as *mut u8;

/// OCD Register 0.
pub const OCDR0: *mut u8 = 0x0 as *mut u8;

/// Lock Bits.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | BLBB | 11000000 |
/// | LB | 11 |
/// | BLBA | 110000 |
/// | BLBAT | 1100 |
pub const LOCKBITS: *mut u8 = 0x0 as *mut u8;

/// Device ID byte 0.
pub const DEVID0: *mut u8 = 0x0 as *mut u8;

/// Event Channel 0 Multiplexer.
pub const CH0MUX: *mut u8 = 0x0 as *mut u8;

/// Analog Comparator 0 Control.
pub const AC0CTRL: *mut u8 = 0x0 as *mut u8;

/// General Purpose IO Register 1.
pub const GPIOR1: *mut u8 = 0x1 as *mut u8;

/// Power Reduction Port A.
pub const PRPA: *mut u8 = 0x1 as *mut u8;

/// RCOSC 2 MHz Calibration Value A.
pub const RCOSC2MA: *mut u8 = 0x1 as *mut u8;

/// Address Register 1.
pub const ADDR1: *mut u8 = 0x1 as *mut u8;

/// Interrupt Priority.
pub const INTPRI: *mut u8 = 0x1 as *mut u8;

/// MUX Control.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | MUXINT | 1111000 |
pub const MUXCTRL: *mut u8 = 0x1 as *mut u8;

/// Analog Comparator 1 Control.
pub const AC1CTRL: *mut u8 = 0x1 as *mut u8;

/// Device ID byte 1.
pub const DEVID1: *mut u8 = 0x1 as *mut u8;

/// Interrupt Control Register.
pub const INTCTRL: *mut u8 = 0x1 as *mut u8;

/// Watchdog Configuration.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | WDWP | 11110000 |
/// | WDP | 1111 |
pub const FUSEBYTE1: *mut u8 = 0x1 as *mut u8;

/// I/O Port Data Direction Set.
pub const DIRSET: *mut u8 = 0x1 as *mut u8;

/// OCD Register 1.
pub const OCDR1: *mut u8 = 0x1 as *mut u8;

/// Event Channel 1 Multiplexer.
pub const CH1MUX: *mut u8 = 0x1 as *mut u8;

/// Prescaler Control Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | PSADIV | 1111100 |
/// | PSBCDIV | 11 |
pub const PSCTRL: *mut u8 = 0x1 as *mut u8;

/// IrDA Transmitter Pulse Length Control Register.
pub const TXPLCTRL: *mut u8 = 0x1 as *mut u8;

/// Device ID byte 2.
pub const DEVID2: *mut u8 = 0x2 as *mut u8;

/// Virtual Port Control Register A.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | VP1MAP | 11110000 |
/// | VP0MAP | 1111 |
pub const VPCTRLA: *mut u8 = 0x2 as *mut u8;

/// Fault Detection Event Mask.
pub const FDEMASK: *mut u8 = 0x2 as *mut u8;

/// Power Reduction Port B.
pub const PRPB: *mut u8 = 0x2 as *mut u8;

/// I/O Port Data Direction Clear.
pub const DIRCLR: *mut u8 = 0x2 as *mut u8;

/// RCOSC 32.768 kHz Calibration Value.
pub const RCOSC32K: *mut u8 = 0x2 as *mut u8;

/// Analog Comparator 0 MUX Control.
pub const AC0MUXCTRL: *mut u8 = 0x2 as *mut u8;

/// Status Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | IF | 10000000 |
/// | WRCOL | 1000000 |
pub const STATUS: *mut u8 = 0x2 as *mut u8;

/// AES State Register.
pub const STATE: *mut u8 = 0x2 as *mut u8;

/// Reset Configuration.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | BODPD | 11 |
/// | TOSCSEL | 100000 |
/// | BOOTRST | 1000000 |
pub const FUSEBYTE2: *mut u8 = 0x2 as *mut u8;

/// Address Register 2.
pub const ADDR2: *mut u8 = 0x2 as *mut u8;

/// Event Channel 2 Multiplexer.
pub const CH2MUX: *mut u8 = 0x2 as *mut u8;

/// Lock register.
pub const LOCK: *mut u8 = 0x2 as *mut u8;

/// IrDA Receiver Pulse Length Control Register.
pub const RXPLCTRL: *mut u8 = 0x2 as *mut u8;

/// Calibration Register A.
pub const CALA: *mut u8 = 0x2 as *mut u8;

/// Reference Control.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | REFSEL | 1110000 |
/// | BANDGAP | 10 |
/// | TEMPREF | 1 |
pub const REFCTRL: *mut u8 = 0x2 as *mut u8;

/// Address Control.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | SRCDIR | 110000 |
/// | SRCRELOAD | 11000000 |
/// | DESTDIR | 11 |
/// | DESTRELOAD | 1100 |
pub const ADDRCTRL: *mut u8 = 0x2 as *mut u8;

/// External Oscillator Control Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | XOSCSEL | 1111 |
/// | FRQRANGE | 11000000 |
/// | XOSCPWR | 10000 |
/// | X32KLPM | 100000 |
pub const XOSCCTRL: *mut u8 = 0x2 as *mut u8;

/// General Purpose IO Register 2.
pub const GPIOR2: *mut u8 = 0x2 as *mut u8;

/// Channel Trigger Source.
pub const TRIGSRC: *mut u8 = 0x3 as *mut u8;

/// Event Channel 3 Multiplexer.
pub const CH3MUX: *mut u8 = 0x3 as *mut u8;

/// Calibration Register B.
pub const CALB: *mut u8 = 0x3 as *mut u8;

/// Control Register A.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | TXCINTLVL | 1100 |
/// | DREINTLVL | 11 |
/// | RXCINTLVL | 110000 |
pub const CTRLA: *mut u8 = 0x3 as *mut u8;

/// Analog Comparator 1 MUX Control.
pub const AC1MUXCTRL: *mut u8 = 0x3 as *mut u8;

/// Data Input.
pub const DATAIN: *mut u8 = 0x3 as *mut u8;

/// AES Key Register.
pub const KEY: *mut u8 = 0x3 as *mut u8;

/// Oscillator Failure Detection Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | PLLFDEN | 100 |
/// | XOSCFDIF | 10 |
/// | XOSCFDEN | 1 |
/// | PLLFDIF | 1000 |
pub const XOSCFAIL: *mut u8 = 0x3 as *mut u8;

/// Fault Detection Control Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | FDACT | 11 |
/// | FDMODE | 100 |
/// | FDDBD | 10000 |
pub const FDCTRL: *mut u8 = 0x3 as *mut u8;

/// Control Register D.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | EVACT | 11100000 |
/// | EVDLY | 10000 |
pub const CTRLD: *mut u8 = 0x3 as *mut u8;

/// Virtual Port Control Register B.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | VP2MAP | 1111 |
/// | VP3MAP | 11110000 |
pub const VPCTRLB: *mut u8 = 0x3 as *mut u8;

/// RTC Control Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | RTCEN | 1 |
/// | RTCSRC | 1110 |
pub const RTCCTRL: *mut u8 = 0x3 as *mut u8;

/// Power Reduction Port C.
pub const PRPC: *mut u8 = 0x3 as *mut u8;

/// Event Input Control.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | EVSPLIT | 1000 |
pub const EVCTRL: *mut u8 = 0x3 as *mut u8;

/// I/O Port Data Direction Toggle.
pub const DIRTGL: *mut u8 = 0x3 as *mut u8;

/// Revision ID.
pub const REVID: *mut u8 = 0x3 as *mut u8;

/// Address Register.
pub const ADDR: *mut u8 = 0x3 as *mut u8;

/// General Purpose IO Register 3.
pub const GPIOR3: *mut u8 = 0x3 as *mut u8;

/// Data Register.
pub const DATA: *mut u8 = 0x3 as *mut u8;

/// RCOSC 32 MHz Calibration Value B.
pub const RCOSC32M: *mut u8 = 0x3 as *mut u8;

/// JTAG User ID.
pub const JTAGUID: *mut u8 = 0x4 as *mut u8;

/// Clock Prescaler.
pub const PRESCALER: *mut u8 = 0x4 as *mut u8;

/// Channel Result.
pub const RES: *mut u16 = 0x4 as *mut u16;

/// Control Register B.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | MPCM | 10 |
/// | TXEN | 1000 |
/// | RXEN | 10000 |
/// | TXB8 | 1 |
/// | CLK2X | 100 |
pub const CTRLB: *mut u8 = 0x4 as *mut u8;

/// Data Pointer.
pub const DATAPTR: *mut u16 = 0x4 as *mut u16;

/// Data Register 0.
pub const DATA0: *mut u8 = 0x4 as *mut u8;

/// FIFO Write Pointer Register.
pub const FIFOWP: *mut u8 = 0x4 as *mut u8;

/// Power Reduction Port D.
pub const PRPD: *mut u8 = 0x4 as *mut u8;

/// RCOSC 32 MHz Calibration Value A.
pub const RCOSC32MA: *mut u8 = 0x4 as *mut u8;

/// Control Register E.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | BYTEM | 11 |
pub const CTRLE: *mut u8 = 0x4 as *mut u8;

/// 32.768 kHz Internal Oscillator Calibration Register.
pub const RC32KCAL: *mut u8 = 0x4 as *mut u8;

/// Channel Result low byte.
pub const RESL: *mut u8 = 0x4 as *mut u8;

/// Checksum byte 0.
pub const CHECKSUM0: *mut u8 = 0x4 as *mut u8;

/// Event Channel 4 Multiplexer.
pub const CH4MUX: *mut u8 = 0x4 as *mut u8;

/// General Purpose IO Register 4.
pub const GPIOR4: *mut u8 = 0x4 as *mut u8;

/// I/O Port Output.
pub const OUT: *mut u8 = 0x4 as *mut u8;

/// Oscillator Compare Register 0.
pub const COMP0: *mut u8 = 0x4 as *mut u8;

/// Channel Block Transfer Count.
pub const TRFCNT: *mut u16 = 0x4 as *mut u16;

/// Clock and Event Out Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | CLKOUTSEL | 1100 |
/// | CLKEVPIN | 10000000 |
/// | RTCOUT | 1000000 |
/// | EVOUT | 110000 |
/// | CLKOUT | 11 |
pub const CLKEVOUT: *mut u8 = 0x4 as *mut u8;

/// Start-up Configuration.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | SUT | 1100 |
/// | RSTDISBL | 10000 |
/// | WDLOCK | 10 |
pub const FUSEBYTE4: *mut u8 = 0x4 as *mut u8;

/// USB Control Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | USBSRC | 110 |
/// | USBSEN | 1 |
/// | USBPSDIV | 111000 |
pub const USBCTRL: *mut u8 = 0x4 as *mut u8;

/// Data Pointer low byte.
pub const DATAPTRL: *mut u8 = 0x4 as *mut u8;

/// Configuration Change Protection.
pub const CCP: *mut u8 = 0x4 as *mut u8;

/// Channel Block Transfer Count low byte.
pub const TRFCNTL: *mut u8 = 0x4 as *mut u8;

/// Baurd Rate Control Register.
pub const BAUD: *mut u8 = 0x4 as *mut u8;

/// I/O Port Output Set.
pub const OUTSET: *mut u8 = 0x5 as *mut u8;

/// FIFO Read Pointer Register.
pub const FIFORP: *mut u8 = 0x5 as *mut u8;

/// General Purpose IO Register 5.
pub const GPIOR5: *mut u8 = 0x5 as *mut u8;

/// PLL Control Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | PLLDIV | 100000 |
/// | PLLSRC | 11000000 |
/// | PLLFAC | 11111 |
pub const PLLCTRL: *mut u8 = 0x5 as *mut u8;

/// Oscillator Compare Register 1.
pub const COMP1: *mut u8 = 0x5 as *mut u8;

/// Checksum byte 1.
pub const CHECKSUM1: *mut u8 = 0x5 as *mut u8;

/// Data Pointer high byte.
pub const DATAPTRH: *mut u8 = 0x5 as *mut u8;

/// Address Mask Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | ADDREN | 1 |
pub const ADDRMASK: *mut u8 = 0x5 as *mut u8;

/// Channel Result high byte.
pub const RESH: *mut u8 = 0x5 as *mut u8;

/// EESAVE and BOD Level.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | BODLVL | 111 |
/// | BODACT | 110000 |
/// | EESAVE | 1000 |
pub const FUSEBYTE5: *mut u8 = 0x5 as *mut u8;

/// Status Set Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | DTHSBUFV | 10 |
/// | FDF | 100 |
/// | DTLSBUFV | 1 |
pub const STATUSSET: *mut u8 = 0x5 as *mut u8;

/// Event Channel 5 Multiplexer.
pub const CH5MUX: *mut u8 = 0x5 as *mut u8;

/// Control Register C.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | CMODE | 11000000 |
/// | CHSIZE | 111 |
/// | PMODE | 110000 |
/// | SBMODE | 1000 |
pub const CTRLC: *mut u8 = 0x5 as *mut u8;

/// Data Register 1.
pub const DATA1: *mut u8 = 0x5 as *mut u8;

/// Power Reduction Port E.
pub const PRPE: *mut u8 = 0x5 as *mut u8;

/// Channel Block Transfer Count high byte.
pub const TRFCNTH: *mut u8 = 0x5 as *mut u8;

/// Baud Rate Control Register A.
pub const BAUDCTRLA: *mut u8 = 0x6 as *mut u8;

/// Auxiliary Data low byte.
pub const AUXDATAL: *mut u8 = 0x6 as *mut u8;

/// Interrupt Control Register A.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | LUNFINTLVL | 11 |
/// | HUNFINTLVL | 1100 |
pub const INTCTRLA: *mut u8 = 0x6 as *mut u8;

/// Auxiliary Data.
pub const AUXDATA: *mut u16 = 0x6 as *mut u16;

/// Checksum byte 2.
pub const CHECKSUM2: *mut u8 = 0x6 as *mut u8;

/// Window Mode Control.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | WEN | 10000 |
/// | WINTMODE | 1100 |
/// | WINTLVL | 11 |
pub const WINCTRL: *mut u8 = 0x6 as *mut u8;

/// MCU Control.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | JTAGD | 1 |
pub const MCUCR: *mut u8 = 0x6 as *mut u8;

/// DFLL Control Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | RC32MCREF | 110 |
/// | RC2MCREF | 1 |
pub const DFLLCTRL: *mut u8 = 0x6 as *mut u8;

/// Input Channel Scan.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | OFFSET | 11110000 |
/// | SCANNUM | 1111 |
pub const SCAN: *mut u8 = 0x6 as *mut u8;

/// Channel Repeat Count.
pub const REPCNT: *mut u8 = 0x6 as *mut u8;

/// Oscillator Compare Register 2.
pub const COMP2: *mut u8 = 0x6 as *mut u8;

/// Endpoint Configuration Table Pointer low byte.
pub const EPPTRL: *mut u8 = 0x6 as *mut u8;

/// Event Output Select.
pub const EVOUTSEL: *mut u8 = 0x6 as *mut u8;

/// I/O Port Output Clear.
pub const OUTCLR: *mut u8 = 0x6 as *mut u8;

/// General Purpose IO Register 6.
pub const GPIOR6: *mut u8 = 0x6 as *mut u8;

/// Data Register 2.
pub const DATA2: *mut u8 = 0x6 as *mut u8;

/// Endpoint Configuration Table Pointer.
pub const EPPTR: *mut u16 = 0x6 as *mut u16;

/// Dead Time Both Sides.
pub const DTBOTH: *mut u8 = 0x6 as *mut u8;

/// Power Reduction Port F.
pub const PRPF: *mut u8 = 0x6 as *mut u8;

/// Event Channel 6 Multiplexer.
pub const CH6MUX: *mut u8 = 0x6 as *mut u8;

/// Auxiliary Data high byte.
pub const AUXDATAH: *mut u8 = 0x7 as *mut u8;

/// Event Channel 7 Multiplexer.
pub const CH7MUX: *mut u8 = 0x7 as *mut u8;

/// Analog Startup Delay.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | STARTUPDLYA | 11 |
/// | STARTUPDLYB | 1100 |
pub const ANAINIT: *mut u8 = 0x7 as *mut u8;

/// Endpoint Configuration Table Pointer high byte.
pub const EPPTRH: *mut u8 = 0x7 as *mut u8;

/// Interrupt Control Register B.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | LCMPCINTLVL | 110000 |
/// | LCMPBINTLVL | 1100 |
/// | LCMPDINTLVL | 11000000 |
/// | LCMPAINTLVL | 11 |
pub const INTCTRLB: *mut u8 = 0x7 as *mut u8;

/// Checksum byte 3.
pub const CHECKSUM3: *mut u8 = 0x7 as *mut u8;

/// General Purpose IO Register 7.
pub const GPIOR7: *mut u8 = 0x7 as *mut u8;

/// I/O Port Output Toggle.
pub const OUTTGL: *mut u8 = 0x7 as *mut u8;

/// Baud Rate Control Register B.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | BSCALE | 11110000 |
pub const BAUDCTRLB: *mut u8 = 0x7 as *mut u8;

/// Dead Time Both Sides Buffer.
pub const DTBOTHBUF: *mut u8 = 0x7 as *mut u8;

/// Control Register F Clear.
pub const CTRLFCLR: *mut u8 = 0x8 as *mut u8;

/// Channel Source Address 0.
pub const SRCADDR0: *mut u8 = 0x8 as *mut u8;

/// I/O port Input.
pub const IN: *mut u8 = 0x8 as *mut u8;

/// Gain Calibration.
pub const CH0GAINCAL: *mut u8 = 0x8 as *mut u8;

/// Lot Number Byte 0, ASCII.
pub const LOTNUM0: *mut u8 = 0x8 as *mut u8;

/// Channel 0 Control Register.
pub const CH0CTRL: *mut u8 = 0x8 as *mut u8;

/// Ramp D.
pub const RAMPD: *mut u8 = 0x8 as *mut u8;

/// Dead Time Low Side.
pub const DTLS: *mut u8 = 0x8 as *mut u8;

/// Event System Lock.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | EVSYS0LOCK | 1 |
/// | EVSYS1LOCK | 10000 |
pub const EVSYSLOCK: *mut u8 = 0x8 as *mut u8;

/// General Purpose IO Register 8.
pub const GPIOR8: *mut u8 = 0x8 as *mut u8;

/// Offset Calibration.
pub const CH0OFFSETCAL: *mut u8 = 0x9 as *mut u8;

/// Channel 1 Control Register.
pub const CH1CTRL: *mut u8 = 0x9 as *mut u8;

/// Control Register F.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | CMDEN | 11 |
pub const CTRLF: *mut u8 = 0x9 as *mut u8;

/// General Purpose IO Register 9.
pub const GPIOR9: *mut u8 = 0x9 as *mut u8;

/// Control Register F Set.
pub const CTRLFSET: *mut u8 = 0x9 as *mut u8;

/// AWEX Lock.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | AWEXDLOCK | 10 |
/// | AWEXFLOCK | 1000 |
/// | AWEXCLOCK | 1 |
/// | AWEXELOCK | 100 |
pub const AWEXLOCK: *mut u8 = 0x9 as *mut u8;

/// Lot Number Byte 1, ASCII.
pub const LOTNUM1: *mut u8 = 0x9 as *mut u8;

/// Channel Source Address 1.
pub const SRCADDR1: *mut u8 = 0x9 as *mut u8;

/// Ramp X.
pub const RAMPX: *mut u8 = 0x9 as *mut u8;

/// Dead Time High Side.
pub const DTHS: *mut u8 = 0x9 as *mut u8;

/// Clear Interrupt Flag Register A.
pub const INTFLAGSACLR: *mut u8 = 0xA as *mut u8;

/// Port Interrupt 0 Mask.
pub const INT0MASK: *mut u8 = 0xA as *mut u8;

/// General Purpose IO Register 10.
pub const GPIORA: *mut u8 = 0xA as *mut u8;

/// Lot Number Byte 2, ASCII.
pub const LOTNUM2: *mut u8 = 0xA as *mut u8;

/// Channel Source Address 2.
pub const SRCADDR2: *mut u8 = 0xA as *mut u8;

/// Command.
pub const CMD: *mut u8 = 0xA as *mut u8;

/// Gain Calibration.
pub const CH1GAINCAL: *mut u8 = 0xA as *mut u8;

/// Dead Time Low Side Buffer.
pub const DTLSBUF: *mut u8 = 0xA as *mut u8;

/// Control Register G Clear.
pub const CTRLGCLR: *mut u8 = 0xA as *mut u8;

/// Ramp Y.
pub const RAMPY: *mut u8 = 0xA as *mut u8;

/// Channel 2 Control Register.
pub const CH2CTRL: *mut u8 = 0xA as *mut u8;

/// Ramp Z.
pub const RAMPZ: *mut u8 = 0xB as *mut u8;

/// Channel 3 Control Register.
pub const CH3CTRL: *mut u8 = 0xB as *mut u8;

/// Offset Calibration.
pub const CH1OFFSETCAL: *mut u8 = 0xB as *mut u8;

/// Lot Number Byte 3, ASCII.
pub const LOTNUM3: *mut u8 = 0xB as *mut u8;

/// Set Interrupt Flag Register A.
pub const INTFLAGSASET: *mut u8 = 0xB as *mut u8;

/// General Purpose IO Register 11.
pub const GPIORB: *mut u8 = 0xB as *mut u8;

/// Dead Time High Side Buffer.
pub const DTHSBUF: *mut u8 = 0xB as *mut u8;

/// Control Register G Set.
pub const CTRLGSET: *mut u8 = 0xB as *mut u8;

/// Port Interrupt 1 Mask.
pub const INT1MASK: *mut u8 = 0xB as *mut u8;

/// Interrupt Flag Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | HUNFIF | 10 |
/// | LCMPBIF | 100000 |
/// | LCMPCIF | 1000000 |
/// | LCMPDIF | 10000000 |
/// | LCMPAIF | 10000 |
/// | LUNFIF | 1 |
pub const INTFLAGS: *mut u8 = 0xC as *mut u8;

/// Compare Register.
pub const COMP: *mut u16 = 0xC as *mut u16;

/// Calibration Value.
pub const CAL: *mut u16 = 0xC as *mut u16;

/// Lot Number Byte 4, ASCII.
pub const LOTNUM4: *mut u8 = 0xC as *mut u8;

/// General Purpose IO Register 12.
pub const GPIORC: *mut u8 = 0xC as *mut u8;

/// Output Override Enable.
pub const OUTOVEN: *mut u8 = 0xC as *mut u8;

/// Calibration Value low byte.
pub const CALL: *mut u8 = 0xC as *mut u8;

/// Clear Interrupt Flag Register B.
pub const INTFLAGSBCLR: *mut u8 = 0xC as *mut u8;

/// Channel Destination Address 0.
pub const DESTADDR0: *mut u8 = 0xC as *mut u8;

/// Channel 4 Control Register.
pub const CH4CTRL: *mut u8 = 0xC as *mut u8;

/// Extended Indirect Jump.
pub const EIND: *mut u8 = 0xC as *mut u8;

/// Compare Register low byte.
pub const COMPL: *mut u8 = 0xC as *mut u8;

/// Channel 5 Control Register.
pub const CH5CTRL: *mut u8 = 0xD as *mut u8;

/// General Purpose IO Register 13.
pub const GPIORD: *mut u8 = 0xD as *mut u8;

/// Compare Register high byte.
pub const COMPH: *mut u8 = 0xD as *mut u8;

/// Calibration Value high byte.
pub const CALH: *mut u8 = 0xD as *mut u8;

/// Channel Destination Address 1.
pub const DESTADDR1: *mut u8 = 0xD as *mut u8;

/// Lot Number Byte 5, ASCII.
pub const LOTNUM5: *mut u8 = 0xD as *mut u8;

/// Set Interrupt Flag Register B.
pub const INTFLAGSBSET: *mut u8 = 0xD as *mut u8;

/// Stack Pointer Low.
pub const SPL: *mut u8 = 0xD as *mut u8;

/// Channel Destination Address 2.
pub const DESTADDR2: *mut u8 = 0xE as *mut u8;

/// Stack Pointer High.
pub const SPH: *mut u8 = 0xE as *mut u8;

/// General Purpose IO Register 14.
pub const GPIORE: *mut u8 = 0xE as *mut u8;

/// I/O Port Pin Remap Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | TC0C | 100 |
/// | TC0B | 10 |
/// | TC0A | 1 |
/// | TC0D | 1000 |
pub const REMAP: *mut u8 = 0xE as *mut u8;

/// Channel 6 Control Register.
pub const CH6CTRL: *mut u8 = 0xE as *mut u8;

/// Channel 7 Control Register.
pub const CH7CTRL: *mut u8 = 0xF as *mut u8;

/// Status Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | I | 10000000 |
/// | T | 1000000 |
/// | N | 100 |
/// | S | 10000 |
/// | H | 100000 |
/// | C | 1 |
/// | Z | 10 |
/// | V | 1000 |
pub const SREG: *mut u8 = 0xF as *mut u8;

/// General Purpose IO Register 15.
pub const GPIORF: *mut u8 = 0xF as *mut u8;

/// Temporary Register For 16-bit Access.
pub const TEMP: *mut u8 = 0xF as *mut u8;

/// Event Strobe.
pub const STROBE: *mut u8 = 0x10 as *mut u8;

/// Pin 0 Control Register.
pub const PIN0CTRL: *mut u8 = 0x10 as *mut u8;

/// Channel 0 Result.
pub const CH0RES: *mut u16 = 0x10 as *mut u16;

/// Channel 0 Result low byte.
pub const CH0RESL: *mut u8 = 0x10 as *mut u8;

/// Wafer Number.
pub const WAFNUM: *mut u8 = 0x10 as *mut u8;

/// Pin 1 Control Register.
pub const PIN1CTRL: *mut u8 = 0x11 as *mut u8;

/// Channel 0 Result high byte.
pub const CH0RESH: *mut u8 = 0x11 as *mut u8;

/// Channel 1 Result low byte.
pub const CH1RESL: *mut u8 = 0x12 as *mut u8;

/// Wafer Coordinate X Byte 0.
pub const COORDX0: *mut u8 = 0x12 as *mut u8;

/// Pin 2 Control Register.
pub const PIN2CTRL: *mut u8 = 0x12 as *mut u8;

/// Channel 1 Result.
pub const CH1RES: *mut u16 = 0x12 as *mut u16;

/// Channel 1 Result high byte.
pub const CH1RESH: *mut u8 = 0x13 as *mut u8;

/// Pin 3 Control Register.
pub const PIN3CTRL: *mut u8 = 0x13 as *mut u8;

/// Wafer Coordinate X Byte 1.
pub const COORDX1: *mut u8 = 0x13 as *mut u8;

/// Channel 2 Result low byte.
pub const CH2RESL: *mut u8 = 0x14 as *mut u8;

/// Channel 2 Result.
pub const CH2RES: *mut u16 = 0x14 as *mut u16;

/// Wafer Coordinate Y Byte 0.
pub const COORDY0: *mut u8 = 0x14 as *mut u8;

/// Pin 4 Control Register.
pub const PIN4CTRL: *mut u8 = 0x14 as *mut u8;

/// Channel 2 Result high byte.
pub const CH2RESH: *mut u8 = 0x15 as *mut u8;

/// Wafer Coordinate Y Byte 1.
pub const COORDY1: *mut u8 = 0x15 as *mut u8;

/// Pin 5 Control Register.
pub const PIN5CTRL: *mut u8 = 0x15 as *mut u8;

/// Channel 3 Result.
pub const CH3RES: *mut u16 = 0x16 as *mut u16;

/// Pin 6 Control Register.
pub const PIN6CTRL: *mut u8 = 0x16 as *mut u8;

/// Channel 3 Result low byte.
pub const CH3RESL: *mut u8 = 0x16 as *mut u8;

/// Pin 7 Control Register.
pub const PIN7CTRL: *mut u8 = 0x17 as *mut u8;

/// Channel 3 Result high byte.
pub const CH3RESH: *mut u8 = 0x17 as *mut u8;

/// Compare Value low byte.
pub const CMPL: *mut u8 = 0x18 as *mut u8;

/// Channel 0 Data.
pub const CH0DATA: *mut u16 = 0x18 as *mut u16;

/// Compare Value.
pub const CMP: *mut u16 = 0x18 as *mut u16;

/// Channel 0 Data low byte.
pub const CH0DATAL: *mut u8 = 0x18 as *mut u8;

/// Channel 0 Data high byte.
pub const CH0DATAH: *mut u8 = 0x19 as *mut u8;

/// Compare Value high byte.
pub const CMPH: *mut u8 = 0x19 as *mut u8;

/// USB Calibration Byte 0.
pub const USBCAL0: *mut u8 = 0x1A as *mut u8;

/// Channel 1 Data low byte.
pub const CH1DATAL: *mut u8 = 0x1A as *mut u8;

/// Channel 1 Data.
pub const CH1DATA: *mut u16 = 0x1A as *mut u16;

/// USB Calibration Byte 1.
pub const USBCAL1: *mut u8 = 0x1B as *mut u8;

/// Channel 1 Data high byte.
pub const CH1DATAH: *mut u8 = 0x1B as *mut u8;

/// USB RCOSC Calibration Value B.
pub const USBRCOSC: *mut u8 = 0x1C as *mut u8;

/// USB RCOSC Calibration Value A.
pub const USBRCOSCA: *mut u8 = 0x1D as *mut u8;

/// Low Byte Count.
pub const LCNT: *mut u8 = 0x20 as *mut u8;

/// Count.
pub const CNT: *mut u16 = 0x20 as *mut u16;

/// ADCA Calibration Byte 0.
pub const ADCACAL0: *mut u8 = 0x20 as *mut u8;

/// Count low byte.
pub const CNTL: *mut u8 = 0x20 as *mut u8;

/// ADCA Calibration Byte 1.
pub const ADCACAL1: *mut u8 = 0x21 as *mut u8;

/// Count high byte.
pub const CNTH: *mut u8 = 0x21 as *mut u8;

/// High Byte Count.
pub const HCNT: *mut u8 = 0x21 as *mut u8;

/// ADCB Calibration Byte 0.
pub const ADCBCAL0: *mut u8 = 0x24 as *mut u8;

/// ADCB Calibration Byte 1.
pub const ADCBCAL1: *mut u8 = 0x25 as *mut u8;

/// Period.
pub const PER: *mut u16 = 0x26 as *mut u16;

/// Period low byte.
pub const PERL: *mut u8 = 0x26 as *mut u8;

/// Low Byte Period.
pub const LPER: *mut u8 = 0x26 as *mut u8;

/// High Byte Period.
pub const HPER: *mut u8 = 0x27 as *mut u8;

/// Period high byte.
pub const PERH: *mut u8 = 0x27 as *mut u8;

/// Compare or Capture A.
pub const CCA: *mut u16 = 0x28 as *mut u16;

/// Low Byte Compare A.
pub const LCMPA: *mut u8 = 0x28 as *mut u8;

/// Compare or Capture A low byte.
pub const CCAL: *mut u8 = 0x28 as *mut u8;

/// Compare or Capture A high byte.
pub const CCAH: *mut u8 = 0x29 as *mut u8;

/// High Byte Compare A.
pub const HCMPA: *mut u8 = 0x29 as *mut u8;

/// Low Byte Compare B.
pub const LCMPB: *mut u8 = 0x2A as *mut u8;

/// Compare or Capture B.
pub const CCB: *mut u16 = 0x2A as *mut u16;

/// Compare or Capture B low byte.
pub const CCBL: *mut u8 = 0x2A as *mut u8;

/// High Byte Compare B.
pub const HCMPB: *mut u8 = 0x2B as *mut u8;

/// Compare or Capture B high byte.
pub const CCBH: *mut u8 = 0x2B as *mut u8;

/// Compare or Capture C low byte.
pub const CCCL: *mut u8 = 0x2C as *mut u8;

/// Compare or Capture C.
pub const CCC: *mut u16 = 0x2C as *mut u16;

/// Low Byte Compare C.
pub const LCMPC: *mut u8 = 0x2C as *mut u8;

/// Compare or Capture C high byte.
pub const CCCH: *mut u8 = 0x2D as *mut u8;

/// High Byte Compare C.
pub const HCMPC: *mut u8 = 0x2D as *mut u8;

/// Low Byte Compare D.
pub const LCMPD: *mut u8 = 0x2E as *mut u8;

/// Temperature Sensor Calibration Byte 0.
pub const TEMPSENSE0: *mut u8 = 0x2E as *mut u8;

/// Compare or Capture D.
pub const CCD: *mut u16 = 0x2E as *mut u16;

/// Compare or Capture D low byte.
pub const CCDL: *mut u8 = 0x2E as *mut u8;

/// Compare or Capture D high byte.
pub const CCDH: *mut u8 = 0x2F as *mut u8;

/// Temperature Sensor Calibration Byte 1.
pub const TEMPSENSE1: *mut u8 = 0x2F as *mut u8;

/// High Byte Compare D.
pub const HCMPD: *mut u8 = 0x2F as *mut u8;

/// DACA0 Calibration Byte 0.
pub const DACA0OFFCAL: *mut u8 = 0x30 as *mut u8;

/// DACA0 Calibration Byte 1.
pub const DACA0GAINCAL: *mut u8 = 0x31 as *mut u8;

/// DACB0 Calibration Byte 0.
pub const DACB0OFFCAL: *mut u8 = 0x32 as *mut u8;

/// DACB0 Calibration Byte 1.
pub const DACB0GAINCAL: *mut u8 = 0x33 as *mut u8;

/// DACA1 Calibration Byte 0.
pub const DACA1OFFCAL: *mut u8 = 0x34 as *mut u8;

/// DACA1 Calibration Byte 1.
pub const DACA1GAINCAL: *mut u8 = 0x35 as *mut u8;

/// Period Buffer low byte.
pub const PERBUFL: *mut u8 = 0x36 as *mut u8;

/// DACB1 Calibration Byte 0.
pub const DACB1OFFCAL: *mut u8 = 0x36 as *mut u8;

/// Period Buffer.
pub const PERBUF: *mut u16 = 0x36 as *mut u16;

/// Period Buffer high byte.
pub const PERBUFH: *mut u8 = 0x37 as *mut u8;

/// DACB1 Calibration Byte 1.
pub const DACB1GAINCAL: *mut u8 = 0x37 as *mut u8;

/// Compare Or Capture A Buffer low byte.
pub const CCABUFL: *mut u8 = 0x38 as *mut u8;

/// Compare Or Capture A Buffer.
pub const CCABUF: *mut u16 = 0x38 as *mut u16;

/// Compare Or Capture A Buffer high byte.
pub const CCABUFH: *mut u8 = 0x39 as *mut u8;

/// Calibration Byte 0.
pub const CAL0: *mut u8 = 0x3A as *mut u8;

/// Compare Or Capture B Buffer.
pub const CCBBUF: *mut u16 = 0x3A as *mut u16;

/// Compare Or Capture B Buffer low byte.
pub const CCBBUFL: *mut u8 = 0x3A as *mut u8;

/// Compare Or Capture B Buffer high byte.
pub const CCBBUFH: *mut u8 = 0x3B as *mut u8;

/// Calibration Byte 1.
pub const CAL1: *mut u8 = 0x3B as *mut u8;

/// Compare Or Capture C Buffer.
pub const CCCBUF: *mut u16 = 0x3C as *mut u16;

/// Compare Or Capture C Buffer low byte.
pub const CCCBUFL: *mut u8 = 0x3C as *mut u8;

/// Compare Or Capture C Buffer high byte.
pub const CCCBUFH: *mut u8 = 0x3D as *mut u8;

/// Compare Or Capture D Buffer.
pub const CCDBUF: *mut u16 = 0x3E as *mut u16;

/// Compare Or Capture D Buffer low byte.
pub const CCDBUFL: *mut u8 = 0x3E as *mut u8;

/// Compare Or Capture D Buffer high byte.
pub const CCDBUFH: *mut u8 = 0x3F as *mut u8;

/// Frame Number Low Byte.
pub const FRAMENUML: *mut u8 = 0x110 as *mut u8;

/// Frame Number High Byte.
pub const FRAMENUMH: *mut u8 = 0x111 as *mut u8;

/// Bitfield on register ADDRCTRL
pub const SRCDIR: *mut u8 = 0x30 as *mut u8;

/// Bitfield on register ADDRCTRL
pub const SRCRELOAD: *mut u8 = 0xC0 as *mut u8;

/// Bitfield on register ADDRCTRL
pub const DESTDIR: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register ADDRCTRL
pub const DESTRELOAD: *mut u8 = 0xC as *mut u8;

/// Bitfield on register ADDRMASK
pub const ADDREN: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register ANAINIT
pub const STARTUPDLYA: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register ANAINIT
pub const STARTUPDLYB: *mut u8 = 0xC as *mut u8;

/// Bitfield on register AWEXLOCK
pub const AWEXDLOCK: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register AWEXLOCK
pub const AWEXFLOCK: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register AWEXLOCK
pub const AWEXCLOCK: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register AWEXLOCK
pub const AWEXELOCK: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register BAUDCTRLB
pub const BSCALE: *mut u8 = 0xF0 as *mut u8;

/// Bitfield on register CLKEVOUT
pub const CLKOUTSEL: *mut u8 = 0xC as *mut u8;

/// Bitfield on register CLKEVOUT
pub const CLKEVPIN: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register CLKEVOUT
pub const RTCOUT: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register CLKEVOUT
pub const EVOUT: *mut u8 = 0x30 as *mut u8;

/// Bitfield on register CLKEVOUT
pub const CLKOUT: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register CTRLA
pub const TXCINTLVL: *mut u8 = 0xC as *mut u8;

/// Bitfield on register CTRLA
pub const DREINTLVL: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register CTRLA
pub const RXCINTLVL: *mut u8 = 0x30 as *mut u8;

/// Bitfield on register CTRLB
pub const MPCM: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register CTRLB
pub const TXEN: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register CTRLB
pub const RXEN: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register CTRLB
pub const TXB8: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register CTRLB
pub const CLK2X: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register CTRLC
pub const CMODE: *mut u8 = 0xC0 as *mut u8;

/// Bitfield on register CTRLC
pub const CHSIZE: *mut u8 = 0x7 as *mut u8;

/// Bitfield on register CTRLC
pub const PMODE: *mut u8 = 0x30 as *mut u8;

/// Bitfield on register CTRLC
pub const SBMODE: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register CTRLD
pub const EVACT: *mut u8 = 0xE0 as *mut u8;

/// Bitfield on register CTRLD
pub const EVDLY: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register CTRLE
pub const BYTEM: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register CTRLF
pub const CMDEN: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register DFLLCTRL
pub const RC32MCREF: *mut u8 = 0x6 as *mut u8;

/// Bitfield on register DFLLCTRL
pub const RC2MCREF: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register EVCTRL
pub const EVSPLIT: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register EVSYSLOCK
pub const EVSYS0LOCK: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register EVSYSLOCK
pub const EVSYS1LOCK: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register FDCTRL
pub const FDACT: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register FDCTRL
pub const FDMODE: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register FDCTRL
pub const FDDBD: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register FUSEBYTE1
pub const WDWP: *mut u8 = 0xF0 as *mut u8;

/// Bitfield on register FUSEBYTE1
pub const WDP: *mut u8 = 0xF as *mut u8;

/// Bitfield on register FUSEBYTE2
pub const BODPD: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register FUSEBYTE2
pub const TOSCSEL: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register FUSEBYTE2
pub const BOOTRST: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register FUSEBYTE4
pub const SUT: *mut u8 = 0xC as *mut u8;

/// Bitfield on register FUSEBYTE4
pub const RSTDISBL: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register FUSEBYTE4
pub const WDLOCK: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register FUSEBYTE5
pub const BODLVL: *mut u8 = 0x7 as *mut u8;

/// Bitfield on register FUSEBYTE5
pub const BODACT: *mut u8 = 0x30 as *mut u8;

/// Bitfield on register FUSEBYTE5
pub const EESAVE: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register INTCTRLA
pub const LUNFINTLVL: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register INTCTRLA
pub const HUNFINTLVL: *mut u8 = 0xC as *mut u8;

/// Bitfield on register INTCTRLB
pub const LCMPCINTLVL: *mut u8 = 0x30 as *mut u8;

/// Bitfield on register INTCTRLB
pub const LCMPBINTLVL: *mut u8 = 0xC as *mut u8;

/// Bitfield on register INTCTRLB
pub const LCMPDINTLVL: *mut u8 = 0xC0 as *mut u8;

/// Bitfield on register INTCTRLB
pub const LCMPAINTLVL: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register INTFLAGS
pub const HUNFIF: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register INTFLAGS
pub const LCMPBIF: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register INTFLAGS
pub const LCMPCIF: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register INTFLAGS
pub const LCMPDIF: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register INTFLAGS
pub const LCMPAIF: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register INTFLAGS
pub const LUNFIF: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register LOCKBITS
pub const BLBB: *mut u8 = 0xC0 as *mut u8;

/// Bitfield on register LOCKBITS
pub const LB: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register LOCKBITS
pub const BLBA: *mut u8 = 0x30 as *mut u8;

/// Bitfield on register LOCKBITS
pub const BLBAT: *mut u8 = 0xC as *mut u8;

/// Bitfield on register MCUCR
pub const JTAGD: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register MUXCTRL
pub const MUXINT: *mut u8 = 0x78 as *mut u8;

/// Bitfield on register PLLCTRL
pub const PLLDIV: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register PLLCTRL
pub const PLLSRC: *mut u8 = 0xC0 as *mut u8;

/// Bitfield on register PLLCTRL
pub const PLLFAC: *mut u8 = 0x1F as *mut u8;

/// Bitfield on register PRGEN
pub const EVSYS: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register PRGEN
pub const RTC: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register PRGEN
pub const DMA: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register PRGEN
pub const USB: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register PRGEN
pub const AES: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register PSCTRL
pub const PSADIV: *mut u8 = 0x7C as *mut u8;

/// Bitfield on register PSCTRL
pub const PSBCDIV: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register REFCTRL
pub const REFSEL: *mut u8 = 0x70 as *mut u8;

/// Bitfield on register REFCTRL
pub const BANDGAP: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register REFCTRL
pub const TEMPREF: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register REMAP
pub const TC0C: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register REMAP
pub const TC0B: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register REMAP
pub const TC0A: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register REMAP
pub const TC0D: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register RTCCTRL
pub const RTCEN: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register RTCCTRL
pub const RTCSRC: *mut u8 = 0xE as *mut u8;

/// Bitfield on register SCAN
pub const OFFSET: *mut u8 = 0xF0 as *mut u8;

/// Bitfield on register SCAN
pub const SCANNUM: *mut u8 = 0xF as *mut u8;

/// Bitfield on register SREG
pub const I: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register SREG
pub const T: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register SREG
pub const N: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register SREG
pub const S: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register SREG
pub const H: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register SREG
pub const C: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register SREG
pub const Z: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register SREG
pub const V: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register STATUS
pub const IF: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register STATUS
pub const WRCOL: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register STATUSSET
pub const DTHSBUFV: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register STATUSSET
pub const FDF: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register STATUSSET
pub const DTLSBUFV: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register USBCTRL
pub const USBSRC: *mut u8 = 0x6 as *mut u8;

/// Bitfield on register USBCTRL
pub const USBSEN: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register USBCTRL
pub const USBPSDIV: *mut u8 = 0x38 as *mut u8;

/// Bitfield on register VPCTRLA
pub const VP1MAP: *mut u8 = 0xF0 as *mut u8;

/// Bitfield on register VPCTRLA
pub const VP0MAP: *mut u8 = 0xF as *mut u8;

/// Bitfield on register VPCTRLB
pub const VP2MAP: *mut u8 = 0xF as *mut u8;

/// Bitfield on register VPCTRLB
pub const VP3MAP: *mut u8 = 0xF0 as *mut u8;

/// Bitfield on register WINCTRL
pub const WEN: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register WINCTRL
pub const WINTMODE: *mut u8 = 0xC as *mut u8;

/// Bitfield on register WINCTRL
pub const WINTLVL: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register XOSCCTRL
pub const XOSCSEL: *mut u8 = 0xF as *mut u8;

/// Bitfield on register XOSCCTRL
pub const FRQRANGE: *mut u8 = 0xC0 as *mut u8;

/// Bitfield on register XOSCCTRL
pub const XOSCPWR: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register XOSCCTRL
pub const X32KLPM: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register XOSCFAIL
pub const PLLFDEN: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register XOSCFAIL
pub const XOSCFDIF: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register XOSCFAIL
pub const XOSCFDEN: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register XOSCFAIL
pub const PLLFDIF: *mut u8 = 0x8 as *mut u8;