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//! The AVR ATtiny24 microcontroller //! //! # Variants //! | | Pinout | Mcuage | Operating temperature | Operating voltage | Max speed | //! |--------|--------|---------|-----------------------|-------------------|-----------| //! | standard | | | 0°C - 0°C | 1.8V - 5.5V | 0 MHz | //! #![allow(non_upper_case_globals)] /// LOCKBIT register /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | LB | 11 | pub const LOCKBIT: *mut u8 = 0x0 as *mut u8; /// LOW register /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | CKOUT | 1000000 | /// | CKDIV8 | 10000000 | /// | SUT_CKSEL | 111111 | pub const LOW: *mut u8 = 0x0 as *mut u8; /// HIGH register /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | WDTON | 10000 | /// | BODLEVEL | 111 | /// | DWEN | 1000000 | /// | RSTDISBL | 10000000 | /// | SPIEN | 100000 | /// | EESAVE | 1000 | pub const HIGH: *mut u8 = 0x1 as *mut u8; /// EXTENDED register /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | SELFPRGEN | 1 | pub const EXTENDED: *mut u8 = 0x2 as *mut u8; /// Power Reduction Register. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | PRTIM0 | 100 | /// | PRADC | 1 | /// | PRTIM1 | 1000 | /// | PRUSI | 10 | pub const PRR: *mut u8 = 0x20 as *mut u8; /// Digital Input Disable Register 0. pub const DIDR0: *mut u8 = 0x21 as *mut u8; /// ADC Control and Status Register B. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | ADTS | 111 | /// | BIN | 10000000 | /// | ADLAR | 10000 | pub const ADCSRB: *mut u8 = 0x23 as *mut u8; /// ADC Data Register Bytes. pub const ADC: *mut u16 = 0x24 as *mut u16; /// ADC Data Register Bytes low byte. pub const ADCL: *mut u8 = 0x24 as *mut u8; /// ADC Data Register Bytes high byte. pub const ADCH: *mut u8 = 0x25 as *mut u8; /// ADC Control and Status Register A. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | ADIE | 1000 | /// | ADIF | 10000 | /// | ADSC | 1000000 | /// | ADATE | 100000 | /// | ADPS | 111 | /// | ADEN | 10000000 | pub const ADCSRA: *mut u8 = 0x26 as *mut u8; /// ADC Multiplexer Selection Register. pub const ADMUX: *mut u8 = 0x27 as *mut u8; /// Analog Comparator Control And Status Register. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | ACIE | 1000 | /// | ACIS | 11 | /// | ACI | 10000 | /// | ACBG | 1000000 | /// | ACD | 10000000 | /// | ACIC | 100 | /// | ACO | 100000 | pub const ACSR: *mut u8 = 0x28 as *mut u8; /// Timer/Counter Interrupt Flag register. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | OCF1B | 100 | /// | TOV1 | 1 | /// | ICF1 | 100000 | /// | OCF1A | 10 | pub const TIFR1: *mut u8 = 0x2B as *mut u8; /// Timer/Counter1 Interrupt Mask Register. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | OCIE1B | 100 | /// | OCIE1A | 10 | /// | ICIE1 | 100000 | /// | TOIE1 | 1 | pub const TIMSK1: *mut u8 = 0x2C as *mut u8; /// USI Control Register. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | USITC | 1 | /// | USICLK | 10 | /// | USICS | 1100 | /// | USIWM | 110000 | /// | USISIE | 10000000 | /// | USIOIE | 1000000 | pub const USICR: *mut u8 = 0x2D as *mut u8; /// USI Status Register. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | USIOIF | 1000000 | /// | USIDC | 10000 | /// | USISIF | 10000000 | /// | USIPF | 100000 | /// | USICNT | 1111 | pub const USISR: *mut u8 = 0x2E as *mut u8; /// USI Data Register. pub const USIDR: *mut u8 = 0x2F as *mut u8; /// USI Buffer Register. pub const USIBR: *mut u8 = 0x30 as *mut u8; /// Pin Change Enable Mask 0. pub const PCMSK0: *mut u8 = 0x32 as *mut u8; /// General Purpose I/O Register 0. pub const GPIOR0: *mut u8 = 0x33 as *mut u8; /// General Purpose I/O Register 1. pub const GPIOR1: *mut u8 = 0x34 as *mut u8; /// General Purpose I/O Register 2. pub const GPIOR2: *mut u8 = 0x35 as *mut u8; /// Input Pins, Port B. pub const PINB: *mut u8 = 0x36 as *mut u8; /// Data Direction Register, Port B. pub const DDRB: *mut u8 = 0x37 as *mut u8; /// Data Register, Port B. pub const PORTB: *mut u8 = 0x38 as *mut u8; /// Port A Input Pins. pub const PINA: *mut u8 = 0x39 as *mut u8; /// Port A Data Direction Register. pub const DDRA: *mut u8 = 0x3A as *mut u8; /// Port A Data Register. pub const PORTA: *mut u8 = 0x3B as *mut u8; /// EEPROM Control Register. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | EERIE | 1000 | /// | EEPE | 10 | /// | EERE | 1 | /// | EEMPE | 100 | /// | EEPM | 110000 | pub const EECR: *mut u8 = 0x3C as *mut u8; /// EEPROM Data Register. pub const EEDR: *mut u8 = 0x3D as *mut u8; /// EEPROM Address Register Bytes. pub const EEAR: *mut u16 = 0x3E as *mut u16; /// EEPROM Address Register Bytes low byte. pub const EEARL: *mut u8 = 0x3E as *mut u8; /// EEPROM Address Register Bytes high byte. pub const EEARH: *mut u8 = 0x3F as *mut u8; /// Pin Change Enable Mask 1. pub const PCMSK1: *mut u8 = 0x40 as *mut u8; /// Watchdog Timer Control Register. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | WDIF | 10000000 | /// | WDCE | 10000 | /// | WDP | 100111 | /// | WDE | 1000 | /// | WDIE | 1000000 | pub const WDTCSR: *mut u8 = 0x41 as *mut u8; /// Timer/Counter1 Control Register C. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | FOC1A | 10000000 | /// | FOC1B | 1000000 | pub const TCCR1C: *mut u8 = 0x42 as *mut u8; /// General Timer/Counter Control Register. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | PSR10 | 1 | /// | TSM | 10000000 | pub const GTCCR: *mut u8 = 0x43 as *mut u8; /// Timer/Counter1 Input Capture Register Bytes low byte. pub const ICR1L: *mut u8 = 0x44 as *mut u8; /// Timer/Counter1 Input Capture Register Bytes. pub const ICR1: *mut u16 = 0x44 as *mut u16; /// Timer/Counter1 Input Capture Register Bytes high byte. pub const ICR1H: *mut u8 = 0x45 as *mut u8; /// Clock Prescale Register. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | CLKPCE | 10000000 | /// | CLKPS | 1111 | pub const CLKPR: *mut u8 = 0x46 as *mut u8; /// Timer/Counter1 Output Compare Register B Bytes low byte. pub const OCR1BL: *mut u8 = 0x48 as *mut u8; /// Timer/Counter1 Output Compare Register B Bytes. pub const OCR1B: *mut u16 = 0x48 as *mut u16; /// Timer/Counter1 Output Compare Register B Bytes high byte. pub const OCR1BH: *mut u8 = 0x49 as *mut u8; /// Timer/Counter1 Output Compare Register A Bytes. pub const OCR1A: *mut u16 = 0x4A as *mut u16; /// Timer/Counter1 Output Compare Register A Bytes low byte. pub const OCR1AL: *mut u8 = 0x4A as *mut u8; /// Timer/Counter1 Output Compare Register A Bytes high byte. pub const OCR1AH: *mut u8 = 0x4B as *mut u8; /// Timer/Counter1 Bytes. pub const TCNT1: *mut u16 = 0x4C as *mut u16; /// Timer/Counter1 Bytes low byte. pub const TCNT1L: *mut u8 = 0x4C as *mut u8; /// Timer/Counter1 Bytes high byte. pub const TCNT1H: *mut u8 = 0x4D as *mut u8; /// Timer/Counter1 Control Register B. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | ICNC1 | 10000000 | /// | ICES1 | 1000000 | /// | CS1 | 111 | pub const TCCR1B: *mut u8 = 0x4E as *mut u8; /// Timer/Counter1 Control Register A. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | COM1A | 11000000 | /// | COM1B | 110000 | pub const TCCR1A: *mut u8 = 0x4F as *mut u8; /// Timer/Counter Control Register A. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | COM0A | 11000000 | /// | COM0B | 110000 | /// | WGM0 | 11 | pub const TCCR0A: *mut u8 = 0x50 as *mut u8; /// Oscillator Calibration Value. pub const OSCCAL: *mut u8 = 0x51 as *mut u8; /// Timer/Counter0. pub const TCNT0: *mut u8 = 0x52 as *mut u8; /// Timer/Counter Control Register B. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | CS0 | 111 | /// | FOC0B | 1000000 | /// | WGM02 | 1000 | /// | FOC0A | 10000000 | pub const TCCR0B: *mut u8 = 0x53 as *mut u8; /// MCU Status Register. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | EXTRF | 10 | /// | BORF | 100 | /// | WDRF | 1000 | /// | PORF | 1 | pub const MCUSR: *mut u8 = 0x54 as *mut u8; /// MCU Control Register. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | PUD | 1000000 | /// | SE | 100000 | /// | SM | 11000 | pub const MCUCR: *mut u8 = 0x55 as *mut u8; /// Timer/Counter0 Output Compare Register A. pub const OCR0A: *mut u8 = 0x56 as *mut u8; /// Store Program Memory Control Register. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | CTPB | 10000 | /// | RFLB | 1000 | /// | SPMEN | 1 | /// | PGWRT | 100 | /// | PGERS | 10 | pub const SPMCSR: *mut u8 = 0x57 as *mut u8; /// Timer/Counter0 Interrupt Flag Register. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | TOV0 | 1 | /// | OCF0B | 100 | /// | OCF0A | 10 | pub const TIFR0: *mut u8 = 0x58 as *mut u8; /// Timer/Counter Interrupt Mask Register. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | OCIE0B | 100 | /// | OCIE0A | 10 | /// | TOIE0 | 1 | pub const TIMSK0: *mut u8 = 0x59 as *mut u8; /// General Interrupt Flag register. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | INTF0 | 1000000 | /// | PCIF | 110000 | pub const GIFR: *mut u8 = 0x5A as *mut u8; /// General Interrupt Mask Register. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | PCIE | 110000 | /// | INT0 | 1000000 | pub const GIMSK: *mut u8 = 0x5B as *mut u8; /// Timer/Counter0 Output Compare Register B. pub const OCR0B: *mut u8 = 0x5C as *mut u8; /// Stack Pointer Low. pub const SPL: *mut u8 = 0x5D as *mut u8; /// Status Register. /// /// Bitfields: /// /// | Name | Mask (binary) | /// | ---- | ------------- | /// | C | 1 | /// | N | 100 | /// | H | 100000 | /// | S | 10000 | /// | V | 1000 | /// | T | 1000000 | /// | Z | 10 | /// | I | 10000000 | pub const SREG: *mut u8 = 0x5F as *mut u8; /// Bitfield on register ACSR pub const ACIE: *mut u8 = 0x8 as *mut u8; /// Bitfield on register ACSR pub const ACIS: *mut u8 = 0x3 as *mut u8; /// Bitfield on register ACSR pub const ACI: *mut u8 = 0x10 as *mut u8; /// Bitfield on register ACSR pub const ACBG: *mut u8 = 0x40 as *mut u8; /// Bitfield on register ACSR pub const ACD: *mut u8 = 0x80 as *mut u8; /// Bitfield on register ACSR pub const ACIC: *mut u8 = 0x4 as *mut u8; /// Bitfield on register ACSR pub const ACO: *mut u8 = 0x20 as *mut u8; /// Bitfield on register ADCSRA pub const ADIE: *mut u8 = 0x8 as *mut u8; /// Bitfield on register ADCSRA pub const ADIF: *mut u8 = 0x10 as *mut u8; /// Bitfield on register ADCSRA pub const ADSC: *mut u8 = 0x40 as *mut u8; /// Bitfield on register ADCSRA pub const ADATE: *mut u8 = 0x20 as *mut u8; /// Bitfield on register ADCSRA pub const ADPS: *mut u8 = 0x7 as *mut u8; /// Bitfield on register ADCSRA pub const ADEN: *mut u8 = 0x80 as *mut u8; /// Bitfield on register ADCSRB pub const ADTS: *mut u8 = 0x7 as *mut u8; /// Bitfield on register ADCSRB pub const BIN: *mut u8 = 0x80 as *mut u8; /// Bitfield on register ADCSRB pub const ADLAR: *mut u8 = 0x10 as *mut u8; /// Bitfield on register CLKPR pub const CLKPCE: *mut u8 = 0x80 as *mut u8; /// Bitfield on register CLKPR pub const CLKPS: *mut u8 = 0xF as *mut u8; /// Bitfield on register EECR pub const EERIE: *mut u8 = 0x8 as *mut u8; /// Bitfield on register EECR pub const EEPE: *mut u8 = 0x2 as *mut u8; /// Bitfield on register EECR pub const EERE: *mut u8 = 0x1 as *mut u8; /// Bitfield on register EECR pub const EEMPE: *mut u8 = 0x4 as *mut u8; /// Bitfield on register EECR pub const EEPM: *mut u8 = 0x30 as *mut u8; /// Bitfield on register EXTENDED pub const SELFPRGEN: *mut u8 = 0x1 as *mut u8; /// Bitfield on register GIFR pub const INTF0: *mut u8 = 0x40 as *mut u8; /// Bitfield on register GIFR pub const PCIF: *mut u8 = 0x30 as *mut u8; /// Bitfield on register GIMSK pub const PCIE: *mut u8 = 0x30 as *mut u8; /// Bitfield on register GIMSK pub const INT0: *mut u8 = 0x40 as *mut u8; /// Bitfield on register GTCCR pub const PSR10: *mut u8 = 0x1 as *mut u8; /// Bitfield on register GTCCR pub const TSM: *mut u8 = 0x80 as *mut u8; /// Bitfield on register HIGH pub const WDTON: *mut u8 = 0x10 as *mut u8; /// Bitfield on register HIGH pub const BODLEVEL: *mut u8 = 0x7 as *mut u8; /// Bitfield on register HIGH pub const DWEN: *mut u8 = 0x40 as *mut u8; /// Bitfield on register HIGH pub const RSTDISBL: *mut u8 = 0x80 as *mut u8; /// Bitfield on register HIGH pub const SPIEN: *mut u8 = 0x20 as *mut u8; /// Bitfield on register HIGH pub const EESAVE: *mut u8 = 0x8 as *mut u8; /// Bitfield on register LOCKBIT pub const LB: *mut u8 = 0x3 as *mut u8; /// Bitfield on register LOW pub const CKOUT: *mut u8 = 0x40 as *mut u8; /// Bitfield on register LOW pub const CKDIV8: *mut u8 = 0x80 as *mut u8; /// Bitfield on register LOW pub const SUT_CKSEL: *mut u8 = 0x3F as *mut u8; /// Bitfield on register MCUCR pub const PUD: *mut u8 = 0x40 as *mut u8; /// Bitfield on register MCUCR pub const SE: *mut u8 = 0x20 as *mut u8; /// Bitfield on register MCUCR pub const SM: *mut u8 = 0x18 as *mut u8; /// Bitfield on register MCUSR pub const EXTRF: *mut u8 = 0x2 as *mut u8; /// Bitfield on register MCUSR pub const BORF: *mut u8 = 0x4 as *mut u8; /// Bitfield on register MCUSR pub const WDRF: *mut u8 = 0x8 as *mut u8; /// Bitfield on register MCUSR pub const PORF: *mut u8 = 0x1 as *mut u8; /// Bitfield on register PRR pub const PRTIM0: *mut u8 = 0x4 as *mut u8; /// Bitfield on register PRR pub const PRADC: *mut u8 = 0x1 as *mut u8; /// Bitfield on register PRR pub const PRTIM1: *mut u8 = 0x8 as *mut u8; /// Bitfield on register PRR pub const PRUSI: *mut u8 = 0x2 as *mut u8; /// Bitfield on register SPMCSR pub const CTPB: *mut u8 = 0x10 as *mut u8; /// Bitfield on register SPMCSR pub const RFLB: *mut u8 = 0x8 as *mut u8; /// Bitfield on register SPMCSR pub const SPMEN: *mut u8 = 0x1 as *mut u8; /// Bitfield on register SPMCSR pub const PGWRT: *mut u8 = 0x4 as *mut u8; /// Bitfield on register SPMCSR pub const PGERS: *mut u8 = 0x2 as *mut u8; /// Bitfield on register SREG pub const C: *mut u8 = 0x1 as *mut u8; /// Bitfield on register SREG pub const N: *mut u8 = 0x4 as *mut u8; /// Bitfield on register SREG pub const H: *mut u8 = 0x20 as *mut u8; /// Bitfield on register SREG pub const S: *mut u8 = 0x10 as *mut u8; /// Bitfield on register SREG pub const V: *mut u8 = 0x8 as *mut u8; /// Bitfield on register SREG pub const T: *mut u8 = 0x40 as *mut u8; /// Bitfield on register SREG pub const Z: *mut u8 = 0x2 as *mut u8; /// Bitfield on register SREG pub const I: *mut u8 = 0x80 as *mut u8; /// Bitfield on register TCCR0A pub const COM0A: *mut u8 = 0xC0 as *mut u8; /// Bitfield on register TCCR0A pub const COM0B: *mut u8 = 0x30 as *mut u8; /// Bitfield on register TCCR0A pub const WGM0: *mut u8 = 0x3 as *mut u8; /// Bitfield on register TCCR0B pub const CS0: *mut u8 = 0x7 as *mut u8; /// Bitfield on register TCCR0B pub const FOC0B: *mut u8 = 0x40 as *mut u8; /// Bitfield on register TCCR0B pub const WGM02: *mut u8 = 0x8 as *mut u8; /// Bitfield on register TCCR0B pub const FOC0A: *mut u8 = 0x80 as *mut u8; /// Bitfield on register TCCR1A pub const COM1A: *mut u8 = 0xC0 as *mut u8; /// Bitfield on register TCCR1A pub const COM1B: *mut u8 = 0x30 as *mut u8; /// Bitfield on register TCCR1B pub const ICNC1: *mut u8 = 0x80 as *mut u8; /// Bitfield on register TCCR1B pub const ICES1: *mut u8 = 0x40 as *mut u8; /// Bitfield on register TCCR1B pub const CS1: *mut u8 = 0x7 as *mut u8; /// Bitfield on register TCCR1C pub const FOC1A: *mut u8 = 0x80 as *mut u8; /// Bitfield on register TCCR1C pub const FOC1B: *mut u8 = 0x40 as *mut u8; /// Bitfield on register TIFR0 pub const TOV0: *mut u8 = 0x1 as *mut u8; /// Bitfield on register TIFR0 pub const OCF0B: *mut u8 = 0x4 as *mut u8; /// Bitfield on register TIFR0 pub const OCF0A: *mut u8 = 0x2 as *mut u8; /// Bitfield on register TIFR1 pub const OCF1B: *mut u8 = 0x4 as *mut u8; /// Bitfield on register TIFR1 pub const TOV1: *mut u8 = 0x1 as *mut u8; /// Bitfield on register TIFR1 pub const ICF1: *mut u8 = 0x20 as *mut u8; /// Bitfield on register TIFR1 pub const OCF1A: *mut u8 = 0x2 as *mut u8; /// Bitfield on register TIMSK0 pub const OCIE0B: *mut u8 = 0x4 as *mut u8; /// Bitfield on register TIMSK0 pub const OCIE0A: *mut u8 = 0x2 as *mut u8; /// Bitfield on register TIMSK0 pub const TOIE0: *mut u8 = 0x1 as *mut u8; /// Bitfield on register TIMSK1 pub const OCIE1B: *mut u8 = 0x4 as *mut u8; /// Bitfield on register TIMSK1 pub const OCIE1A: *mut u8 = 0x2 as *mut u8; /// Bitfield on register TIMSK1 pub const ICIE1: *mut u8 = 0x20 as *mut u8; /// Bitfield on register TIMSK1 pub const TOIE1: *mut u8 = 0x1 as *mut u8; /// Bitfield on register USICR pub const USITC: *mut u8 = 0x1 as *mut u8; /// Bitfield on register USICR pub const USICLK: *mut u8 = 0x2 as *mut u8; /// Bitfield on register USICR pub const USICS: *mut u8 = 0xC as *mut u8; /// Bitfield on register USICR pub const USIWM: *mut u8 = 0x30 as *mut u8; /// Bitfield on register USICR pub const USISIE: *mut u8 = 0x80 as *mut u8; /// Bitfield on register USICR pub const USIOIE: *mut u8 = 0x40 as *mut u8; /// Bitfield on register USISR pub const USIOIF: *mut u8 = 0x40 as *mut u8; /// Bitfield on register USISR pub const USIDC: *mut u8 = 0x10 as *mut u8; /// Bitfield on register USISR pub const USISIF: *mut u8 = 0x80 as *mut u8; /// Bitfield on register USISR pub const USIPF: *mut u8 = 0x20 as *mut u8; /// Bitfield on register USISR pub const USICNT: *mut u8 = 0xF as *mut u8; /// Bitfield on register WDTCSR pub const WDIF: *mut u8 = 0x80 as *mut u8; /// Bitfield on register WDTCSR pub const WDCE: *mut u8 = 0x10 as *mut u8; /// Bitfield on register WDTCSR pub const WDP: *mut u8 = 0x27 as *mut u8; /// Bitfield on register WDTCSR pub const WDE: *mut u8 = 0x8 as *mut u8; /// Bitfield on register WDTCSR pub const WDIE: *mut u8 = 0x40 as *mut u8;