//! The AVR ATmega8535 microcontroller
//!
//! # Variants
//! |        | Pinout | Mcuage | Operating temperature | Operating voltage | Max speed |
//! |--------|--------|---------|-----------------------|-------------------|-----------|
//! | standard |  |  | 0°C - 0°C | 2.7V - 5.5V | 0 MHz |
//!

#![allow(non_upper_case_globals)]

/// LOCKBIT register
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | BLB1 | 110000 |
/// | LB | 11 |
/// | BLB0 | 1100 |
pub const LOCKBIT: *mut u8 = 0x0 as *mut u8;

/// LOW register
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | SUT_CKSEL | 111111 |
/// | BODEN | 1000000 |
/// | BODLEVEL | 10000000 |
pub const LOW: *mut u8 = 0x0 as *mut u8;

/// HIGH register
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | CKOPT | 10000 |
/// | BOOTRST | 1 |
/// | S8535C | 10000000 |
/// | BOOTSZ | 110 |
/// | WDTON | 1000000 |
/// | SPIEN | 100000 |
/// | EESAVE | 1000 |
pub const HIGH: *mut u8 = 0x1 as *mut u8;

/// TWI Bit Rate register.
pub const TWBR: *mut u8 = 0x20 as *mut u8;

/// TWI Status Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | TWS | 11111000 |
/// | TWPS | 11 |
pub const TWSR: *mut u8 = 0x21 as *mut u8;

/// TWI (Slave) Address register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | TWGCE | 1 |
/// | TWA | 11111110 |
pub const TWAR: *mut u8 = 0x22 as *mut u8;

/// TWI Data register.
pub const TWDR: *mut u8 = 0x23 as *mut u8;

/// ADC Data Register  Bytes low byte.
pub const ADCL: *mut u8 = 0x24 as *mut u8;

/// ADC Data Register  Bytes.
pub const ADC: *mut u16 = 0x24 as *mut u16;

/// ADC Data Register  Bytes high byte.
pub const ADCH: *mut u8 = 0x25 as *mut u8;

/// The ADC Control and Status register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | ADPS | 111 |
/// | ADIE | 1000 |
/// | ADSC | 1000000 |
/// | ADIF | 10000 |
/// | ADATE | 100000 |
/// | ADEN | 10000000 |
pub const ADCSRA: *mut u8 = 0x26 as *mut u8;

/// The ADC multiplexer Selection Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | ADLAR | 100000 |
/// | MUX | 11111 |
/// | REFS | 11000000 |
pub const ADMUX: *mut u8 = 0x27 as *mut u8;

/// Analog Comparator Control And Status Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | ACIE | 1000 |
/// | ACI | 10000 |
/// | ACD | 10000000 |
/// | ACIS | 11 |
/// | ACO | 100000 |
/// | ACBG | 1000000 |
/// | ACIC | 100 |
pub const ACSR: *mut u8 = 0x28 as *mut u8;

/// USART Baud Rate Register Low Byte.
pub const UBRRL: *mut u8 = 0x29 as *mut u8;

/// USART Control and Status Register B.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | TXEN | 1000 |
/// | UDRIE | 100000 |
/// | RXCIE | 10000000 |
/// | RXEN | 10000 |
/// | RXB8 | 10 |
/// | TXCIE | 1000000 |
/// | TXB8 | 1 |
/// | UCSZ2 | 100 |
pub const UCSRB: *mut u8 = 0x2A as *mut u8;

/// USART Control and Status Register A.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | TXC | 1000000 |
/// | UDRE | 100000 |
/// | UPE | 100 |
/// | FE | 10000 |
/// | RXC | 10000000 |
/// | MPCM | 1 |
/// | U2X | 10 |
/// | DOR | 1000 |
pub const UCSRA: *mut u8 = 0x2B as *mut u8;

/// USART I/O Data Register.
pub const UDR: *mut u8 = 0x2C as *mut u8;

/// SPI Control Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | CPHA | 100 |
/// | SPIE | 10000000 |
/// | CPOL | 1000 |
/// | SPE | 1000000 |
/// | MSTR | 10000 |
/// | DORD | 100000 |
/// | SPR | 11 |
pub const SPCR: *mut u8 = 0x2D as *mut u8;

/// SPI Status Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | WCOL | 1000000 |
/// | SPIF | 10000000 |
/// | SPI2X | 1 |
pub const SPSR: *mut u8 = 0x2E as *mut u8;

/// SPI Data Register.
pub const SPDR: *mut u8 = 0x2F as *mut u8;

/// Port D Input Pins.
pub const PIND: *mut u8 = 0x30 as *mut u8;

/// Port D Data Direction Register.
pub const DDRD: *mut u8 = 0x31 as *mut u8;

/// Port D Data Register.
pub const PORTD: *mut u8 = 0x32 as *mut u8;

/// Port C Input Pins.
pub const PINC: *mut u8 = 0x33 as *mut u8;

/// Port C Data Direction Register.
pub const DDRC: *mut u8 = 0x34 as *mut u8;

/// Port C Data Register.
pub const PORTC: *mut u8 = 0x35 as *mut u8;

/// Port B Input Pins.
pub const PINB: *mut u8 = 0x36 as *mut u8;

/// Port B Data Direction Register.
pub const DDRB: *mut u8 = 0x37 as *mut u8;

/// Port B Data Register.
pub const PORTB: *mut u8 = 0x38 as *mut u8;

/// Port A Input Pins.
pub const PINA: *mut u8 = 0x39 as *mut u8;

/// Port A Data Direction Register.
pub const DDRA: *mut u8 = 0x3A as *mut u8;

/// Port A Data Register.
pub const PORTA: *mut u8 = 0x3B as *mut u8;

/// EEPROM Control Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | EERE | 1 |
/// | EEWE | 10 |
/// | EERIE | 1000 |
/// | EEMWE | 100 |
pub const EECR: *mut u8 = 0x3C as *mut u8;

/// EEPROM Data Register.
pub const EEDR: *mut u8 = 0x3D as *mut u8;

/// EEPROM Address Register  Bytes low byte.
pub const EEARL: *mut u8 = 0x3E as *mut u8;

/// EEPROM Address Register  Bytes.
pub const EEAR: *mut u16 = 0x3E as *mut u16;

/// EEPROM Address Register  Bytes high byte.
pub const EEARH: *mut u8 = 0x3F as *mut u8;

/// USART Control and Status Register C.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | UCPOL | 1 |
/// | UCSZ | 110 |
/// | UMSEL | 1000000 |
/// | UPM | 110000 |
/// | USBS | 1000 |
pub const UCSRC: *mut u8 = 0x40 as *mut u8;

/// USART Baud Rate Register High Byte.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | UBRR1 | 1100 |
/// | UBRR | 11 |
pub const UBRRH: *mut u8 = 0x40 as *mut u8;

/// Watchdog Timer Control Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | WDCE | 10000 |
/// | WDP | 111 |
/// | WDE | 1000 |
pub const WDTCR: *mut u8 = 0x41 as *mut u8;

/// Asynchronous Status Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | TCR2UB | 1 |
/// | TCN2UB | 100 |
/// | AS2 | 1000 |
/// | OCR2UB | 10 |
pub const ASSR: *mut u8 = 0x42 as *mut u8;

/// Timer/Counter2 Output Compare Register.
pub const OCR2: *mut u8 = 0x43 as *mut u8;

/// Timer/Counter2.
pub const TCNT2: *mut u8 = 0x44 as *mut u8;

/// Timer/Counter2 Control Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | CS2 | 111 |
/// | COM2 | 110000 |
/// | WGM21 | 1000 |
/// | FOC2 | 10000000 |
/// | WGM20 | 1000000 |
pub const TCCR2: *mut u8 = 0x45 as *mut u8;

/// Timer/Counter1 Input Capture Register  Bytes low byte.
pub const ICR1L: *mut u8 = 0x46 as *mut u8;

/// Timer/Counter1 Input Capture Register  Bytes.
pub const ICR1: *mut u16 = 0x46 as *mut u16;

/// Timer/Counter1 Input Capture Register  Bytes high byte.
pub const ICR1H: *mut u8 = 0x47 as *mut u8;

/// Timer/Counter1 Output Compare Register  Bytes low byte.
pub const OCR1BL: *mut u8 = 0x48 as *mut u8;

/// Timer/Counter1 Output Compare Register  Bytes.
pub const OCR1B: *mut u16 = 0x48 as *mut u16;

/// Timer/Counter1 Output Compare Register  Bytes high byte.
pub const OCR1BH: *mut u8 = 0x49 as *mut u8;

/// Timer/Counter1 Output Compare Register  Bytes low byte.
pub const OCR1AL: *mut u8 = 0x4A as *mut u8;

/// Timer/Counter1 Output Compare Register  Bytes.
pub const OCR1A: *mut u16 = 0x4A as *mut u16;

/// Timer/Counter1 Output Compare Register  Bytes high byte.
pub const OCR1AH: *mut u8 = 0x4B as *mut u8;

/// Timer/Counter1  Bytes low byte.
pub const TCNT1L: *mut u8 = 0x4C as *mut u8;

/// Timer/Counter1  Bytes.
pub const TCNT1: *mut u16 = 0x4C as *mut u16;

/// Timer/Counter1  Bytes high byte.
pub const TCNT1H: *mut u8 = 0x4D as *mut u8;

/// Timer/Counter1 Control Register B.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | ICES1 | 1000000 |
/// | CS1 | 111 |
/// | ICNC1 | 10000000 |
pub const TCCR1B: *mut u8 = 0x4E as *mut u8;

/// Timer/Counter1 Control Register A.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | COM1A | 11000000 |
/// | COM1B | 110000 |
/// | FOC1B | 100 |
/// | FOC1A | 1000 |
pub const TCCR1A: *mut u8 = 0x4F as *mut u8;

/// Special Function IO Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | PUD | 100 |
/// | ACME | 1000 |
pub const SFIOR: *mut u8 = 0x50 as *mut u8;

/// Oscillator Calibration Value.
pub const OSCCAL: *mut u8 = 0x51 as *mut u8;

/// Timer/Counter Register.
pub const TCNT0: *mut u8 = 0x52 as *mut u8;

/// Timer/Counter Control Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | WGM00 | 1000000 |
/// | CS0 | 111 |
/// | WGM01 | 1000 |
/// | COM0 | 110000 |
/// | FOC0 | 10000000 |
pub const TCCR0: *mut u8 = 0x53 as *mut u8;

/// MCU Control And Status Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | WDRF | 1000 |
/// | PORF | 1 |
/// | EXTRF | 10 |
/// | BORF | 100 |
pub const MCUCSR: *mut u8 = 0x54 as *mut u8;

/// MCU Control Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | ISC0 | 11 |
/// | SM | 10110000 |
/// | SE | 1000000 |
/// | ISC1 | 1100 |
pub const MCUCR: *mut u8 = 0x55 as *mut u8;

/// TWI Control Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | TWSTA | 100000 |
/// | TWWC | 1000 |
/// | TWEN | 100 |
/// | TWINT | 10000000 |
/// | TWEA | 1000000 |
/// | TWIE | 1 |
/// | TWSTO | 10000 |
pub const TWCR: *mut u8 = 0x56 as *mut u8;

/// SPMCR register
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | SPMEN | 1 |
/// | BLBSET | 1000 |
/// | SPMIE | 10000000 |
/// | PGWRT | 100 |
/// | PGERS | 10 |
/// | RWWSB | 1000000 |
/// | RWWSRE | 10000 |
pub const SPMCR: *mut u8 = 0x57 as *mut u8;

/// Timer/Counter Interrupt Flag Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | TOV2 | 1000000 |
/// | OCF2 | 10000000 |
pub const TIFR: *mut u8 = 0x58 as *mut u8;

/// Timer/Counter Interrupt Mask register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | TOIE2 | 1000000 |
/// | OCIE2 | 10000000 |
pub const TIMSK: *mut u8 = 0x59 as *mut u8;

/// General Interrupt Flag Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | INTF | 11000000 |
/// | INTF2 | 100000 |
pub const GIFR: *mut u8 = 0x5A as *mut u8;

/// General Interrupt Control Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | INT1 | 10000000 |
/// | INT2 | 100000 |
/// | IVCE | 1 |
/// | INT0 | 1000000 |
/// | IVSEL | 10 |
pub const GICR: *mut u8 = 0x5B as *mut u8;

/// Output Compare Register.
pub const OCR0: *mut u8 = 0x5C as *mut u8;

/// Stack Pointer.
pub const SP: *mut u16 = 0x5D as *mut u16;

/// Stack Pointer  low byte.
pub const SPL: *mut u8 = 0x5D as *mut u8;

/// Stack Pointer  high byte.
pub const SPH: *mut u8 = 0x5E as *mut u8;

/// Status Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | V | 1000 |
/// | N | 100 |
/// | S | 10000 |
/// | Z | 10 |
/// | T | 1000000 |
/// | C | 1 |
/// | H | 100000 |
/// | I | 10000000 |
pub const SREG: *mut u8 = 0x5F as *mut u8;

/// Bitfield on register ACSR
pub const ACIE: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register ACSR
pub const ACI: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register ACSR
pub const ACD: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register ACSR
pub const ACIS: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register ACSR
pub const ACO: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register ACSR
pub const ACBG: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register ACSR
pub const ACIC: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register ADCSRA
pub const ADPS: *mut u8 = 0x7 as *mut u8;

/// Bitfield on register ADCSRA
pub const ADIE: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register ADCSRA
pub const ADSC: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register ADCSRA
pub const ADIF: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register ADCSRA
pub const ADATE: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register ADCSRA
pub const ADEN: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register ADMUX
pub const ADLAR: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register ADMUX
pub const MUX: *mut u8 = 0x1F as *mut u8;

/// Bitfield on register ADMUX
pub const REFS: *mut u8 = 0xC0 as *mut u8;

/// Bitfield on register ASSR
pub const TCR2UB: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register ASSR
pub const TCN2UB: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register ASSR
pub const AS2: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register ASSR
pub const OCR2UB: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register EECR
pub const EERE: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register EECR
pub const EEWE: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register EECR
pub const EERIE: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register EECR
pub const EEMWE: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register GICR
pub const INT1: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register GICR
pub const INT2: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register GICR
pub const IVCE: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register GICR
pub const INT0: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register GICR
pub const IVSEL: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register GIFR
pub const INTF: *mut u8 = 0xC0 as *mut u8;

/// Bitfield on register GIFR
pub const INTF2: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register HIGH
pub const CKOPT: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register HIGH
pub const BOOTRST: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register HIGH
pub const S8535C: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register HIGH
pub const BOOTSZ: *mut u8 = 0x6 as *mut u8;

/// Bitfield on register HIGH
pub const WDTON: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register HIGH
pub const SPIEN: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register HIGH
pub const EESAVE: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register LOCKBIT
pub const BLB1: *mut u8 = 0x30 as *mut u8;

/// Bitfield on register LOCKBIT
pub const LB: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register LOCKBIT
pub const BLB0: *mut u8 = 0xC as *mut u8;

/// Bitfield on register LOW
pub const SUT_CKSEL: *mut u8 = 0x3F as *mut u8;

/// Bitfield on register LOW
pub const BODEN: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register LOW
pub const BODLEVEL: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register MCUCR
pub const ISC0: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register MCUCR
pub const SM: *mut u8 = 0xB0 as *mut u8;

/// Bitfield on register MCUCR
pub const SE: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register MCUCR
pub const ISC1: *mut u8 = 0xC as *mut u8;

/// Bitfield on register MCUCSR
pub const WDRF: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register MCUCSR
pub const PORF: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register MCUCSR
pub const EXTRF: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register MCUCSR
pub const BORF: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register SFIOR
pub const PUD: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register SFIOR
pub const ACME: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register SPCR
pub const CPHA: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register SPCR
pub const SPIE: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register SPCR
pub const CPOL: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register SPCR
pub const SPE: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register SPCR
pub const MSTR: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register SPCR
pub const DORD: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register SPCR
pub const SPR: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register SPMCR
pub const SPMEN: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register SPMCR
pub const BLBSET: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register SPMCR
pub const SPMIE: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register SPMCR
pub const PGWRT: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register SPMCR
pub const PGERS: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register SPMCR
pub const RWWSB: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register SPMCR
pub const RWWSRE: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register SPSR
pub const WCOL: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register SPSR
pub const SPIF: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register SPSR
pub const SPI2X: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register SREG
pub const V: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register SREG
pub const N: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register SREG
pub const S: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register SREG
pub const Z: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register SREG
pub const T: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register SREG
pub const C: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register SREG
pub const H: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register SREG
pub const I: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register TCCR0
pub const WGM00: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register TCCR0
pub const CS0: *mut u8 = 0x7 as *mut u8;

/// Bitfield on register TCCR0
pub const WGM01: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register TCCR0
pub const COM0: *mut u8 = 0x30 as *mut u8;

/// Bitfield on register TCCR0
pub const FOC0: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register TCCR1A
pub const COM1A: *mut u8 = 0xC0 as *mut u8;

/// Bitfield on register TCCR1A
pub const COM1B: *mut u8 = 0x30 as *mut u8;

/// Bitfield on register TCCR1A
pub const FOC1B: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register TCCR1A
pub const FOC1A: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register TCCR1B
pub const ICES1: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register TCCR1B
pub const CS1: *mut u8 = 0x7 as *mut u8;

/// Bitfield on register TCCR1B
pub const ICNC1: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register TCCR2
pub const CS2: *mut u8 = 0x7 as *mut u8;

/// Bitfield on register TCCR2
pub const COM2: *mut u8 = 0x30 as *mut u8;

/// Bitfield on register TCCR2
pub const WGM21: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register TCCR2
pub const FOC2: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register TCCR2
pub const WGM20: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register TIFR
pub const TOV2: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register TIFR
pub const OCF2: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register TIMSK
pub const TOIE2: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register TIMSK
pub const OCIE2: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register TWAR
pub const TWGCE: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register TWAR
pub const TWA: *mut u8 = 0xFE as *mut u8;

/// Bitfield on register TWCR
pub const TWSTA: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register TWCR
pub const TWWC: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register TWCR
pub const TWEN: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register TWCR
pub const TWINT: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register TWCR
pub const TWEA: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register TWCR
pub const TWIE: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register TWCR
pub const TWSTO: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register TWSR
pub const TWS: *mut u8 = 0xF8 as *mut u8;

/// Bitfield on register TWSR
pub const TWPS: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register UBRRH
pub const UBRR1: *mut u8 = 0xC as *mut u8;

/// Bitfield on register UBRRH
pub const UBRR: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register UCSRA
pub const TXC: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register UCSRA
pub const UDRE: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register UCSRA
pub const UPE: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register UCSRA
pub const FE: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register UCSRA
pub const RXC: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register UCSRA
pub const MPCM: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register UCSRA
pub const U2X: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register UCSRA
pub const DOR: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register UCSRB
pub const TXEN: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register UCSRB
pub const UDRIE: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register UCSRB
pub const RXCIE: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register UCSRB
pub const RXEN: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register UCSRB
pub const RXB8: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register UCSRB
pub const TXCIE: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register UCSRB
pub const TXB8: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register UCSRB
pub const UCSZ2: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register UCSRC
pub const UCPOL: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register UCSRC
pub const UCSZ: *mut u8 = 0x6 as *mut u8;

/// Bitfield on register UCSRC
pub const UMSEL: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register UCSRC
pub const UPM: *mut u8 = 0x30 as *mut u8;

/// Bitfield on register UCSRC
pub const USBS: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register WDTCR
pub const WDCE: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register WDTCR
pub const WDP: *mut u8 = 0x7 as *mut u8;

/// Bitfield on register WDTCR
pub const WDE: *mut u8 = 0x8 as *mut u8;