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//! The AVR ATtiny43U microcontroller
//!
//! # Variants
//! |        | Pinout | Package | Operating temperature | Operating voltage | Max speed |
//! |--------|--------|---------|-----------------------|-------------------|-----------|
//! | standard |  |  | 0°C - 0°C | 0.7V - 5.5V | 0 MHz |
//!
//! # Registers by module (not exhaustive)
//!
//! ## PORT modules
//!
//! * PORTA
//! * PORTB
//!
//! ## ADC modules
//!
//! * ADC
//!
//! ## EEPROM modules
//!
//! * EEPROM

pub const LOW: *mut u8 = 0x0 as *mut u8;
pub const LOCKBIT: *mut u8 = 0x0 as *mut u8;
pub const HIGH: *mut u8 = 0x1 as *mut u8;
pub const EXTENDED: *mut u8 = 0x2 as *mut u8;
/// Power Reduction Register.
pub const PRR: *mut u8 = 0x20 as *mut u8;
/// Digital Input Disable Register 0.
pub const DIDR0: *mut u8 = 0x21 as *mut u8;
/// ADC Control and Status Register B.
pub const ADCSRB: *mut u8 = 0x23 as *mut u8;
/// ADC Data Register  Bytes.
pub const ADC: *mut u16 = 0x24 as *mut u16;
/// ADC Data Register  Bytes low byte.
pub const ADCL: *mut u8 = 0x24 as *mut u8;
/// ADC Data Register  Bytes high byte.
pub const ADCH: *mut u8 = 0x25 as *mut u8;
/// ADC Control and Status Register A.
pub const ADCSRA: *mut u8 = 0x26 as *mut u8;
/// ADC Multiplexer Selection Register.
pub const ADMUX: *mut u8 = 0x27 as *mut u8;
/// Analog Comparator Control And Status Register.
pub const ACSR: *mut u8 = 0x28 as *mut u8;
/// Timer/Counter1 Interrupt Flag Register.
pub const TIFR1: *mut u8 = 0x2B as *mut u8;
/// Timer/Counter Interrupt Mask Register.
pub const TIMSK1: *mut u8 = 0x2C as *mut u8;
/// USI Control Register.
pub const USICR: *mut u8 = 0x2D as *mut u8;
/// USI Status Register.
pub const USISR: *mut u8 = 0x2E as *mut u8;
/// USI Data Register.
pub const USIDR: *mut u8 = 0x2F as *mut u8;
/// USI Buffer Register.
pub const USIBR: *mut u8 = 0x30 as *mut u8;
/// Pin Change Enable Mask Byte 0.
pub const PCMSK0: *mut u8 = 0x32 as *mut u8;
/// General Purpose I/O Register 0.
pub const GPIOR0: *mut u8 = 0x33 as *mut u8;
/// General Purpose I/O Register 1.
pub const GPIOR1: *mut u8 = 0x34 as *mut u8;
/// General Purpose I/O Register 2.
pub const GPIOR2: *mut u8 = 0x35 as *mut u8;
/// Port B Input Pins.
pub const PINB: *mut u8 = 0x36 as *mut u8;
/// Port B Data Direction Register.
pub const DDRB: *mut u8 = 0x37 as *mut u8;
/// Port B Data Register.
pub const PORTB: *mut u8 = 0x38 as *mut u8;
/// Port A Input Pins.
pub const PINA: *mut u8 = 0x39 as *mut u8;
/// Port A Data Direction Register.
pub const DDRA: *mut u8 = 0x3A as *mut u8;
/// Port A Data Register.
pub const PORTA: *mut u8 = 0x3B as *mut u8;
/// EEPROM Control Register.
pub const EECR: *mut u8 = 0x3C as *mut u8;
/// EEPROM Data Register.
pub const EEDR: *mut u8 = 0x3D as *mut u8;
/// EEPROM Address Register.
pub const EEAR: *mut u8 = 0x3E as *mut u8;
/// Pin Change Enable Mask Byte 1.
pub const PCMSK1: *mut u8 = 0x40 as *mut u8;
/// Watchdog Timer Control Register.
pub const WDTCSR: *mut u8 = 0x41 as *mut u8;
/// General Timer/Counter Control Register.
pub const GTCCR: *mut u8 = 0x43 as *mut u8;
/// Clock Prescale Register.
pub const CLKPR: *mut u8 = 0x46 as *mut u8;
/// Timer/Counter1 Output Compare Register B.
pub const OCR1B: *mut u8 = 0x4B as *mut u8;
/// Timer/Counter1 Output Compare Register A.
pub const OCR1A: *mut u8 = 0x4C as *mut u8;
/// Timer/Counter1.
pub const TCNT1: *mut u8 = 0x4D as *mut u8;
/// Timer/Counter Control Register B.
pub const TCCR1B: *mut u8 = 0x4E as *mut u8;
/// Timer/Counter1 Control Register A.
pub const TCCR1A: *mut u8 = 0x4F as *mut u8;
/// Timer/Counter  Control Register A.
pub const TCCR0A: *mut u8 = 0x50 as *mut u8;
/// Oscillator Calibration Value.
pub const OSCCAL: *mut u8 = 0x51 as *mut u8;
/// Timer/Counter0.
pub const TCNT0: *mut u8 = 0x52 as *mut u8;
/// Timer/Counter Control Register B.
pub const TCCR0B: *mut u8 = 0x53 as *mut u8;
/// MCU Status Register.
pub const MCUSR: *mut u8 = 0x54 as *mut u8;
/// MCU Control Register.
pub const MCUCR: *mut u8 = 0x55 as *mut u8;
/// Timer/Counter0 Output Compare Register A.
pub const OCR0A: *mut u8 = 0x56 as *mut u8;
/// Store Program Memory Control Register.
pub const SPMCSR: *mut u8 = 0x57 as *mut u8;
/// Timer/Counter0 Interrupt Flag Register.
pub const TIFR0: *mut u8 = 0x58 as *mut u8;
/// Timer/Counter Interrupt Mask Register.
pub const TIMSK0: *mut u8 = 0x59 as *mut u8;
/// General Interrupt Flag register.
pub const GIFR: *mut u8 = 0x5A as *mut u8;
/// General Interrupt Mask Register.
pub const GIMSK: *mut u8 = 0x5B as *mut u8;
/// Timer/Counter0 Output Compare Register B.
pub const OCR0B: *mut u8 = 0x5C as *mut u8;
/// Stack Pointer.
pub const SP: *mut u16 = 0x5D as *mut u16;
/// Stack Pointer  low byte.
pub const SPL: *mut u8 = 0x5D as *mut u8;
/// Stack Pointer  high byte.
pub const SPH: *mut u8 = 0x5E as *mut u8;
/// Status Register.
pub const SREG: *mut u8 = 0x5F as *mut u8;