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//! The AVR ATtiny24A microcontroller //! //! # Variants //! | | Pinout | Package | Operating temperature | Operating voltage | Max speed | //! |--------|--------|---------|-----------------------|-------------------|-----------| //! | ATtiny24A-CCU | BGA_16 | UFBGA16 | -40°C - 85°C | 1.8V - 5.5V | 20 MHz | //! | ATtiny24A-MMH | QFN_20 | VQFN20 | -40°C - 85°C | 1.8V - 5.5V | 20 MHz | //! | ATtiny24A-MU | QFN_20 | QFN20 | -40°C - 85°C | 1.8V - 5.5V | 20 MHz | //! | ATtiny24A-PU | SOIC_14 | PDIP14 | -40°C - 85°C | 1.8V - 5.5V | 20 MHz | //! | ATtiny24A-SSU | SOIC_14 | SOIC14 | -40°C - 85°C | 1.8V - 5.5V | 20 MHz | //! | ATtiny24A-SSN | SOIC_14 | SOIC14 | -40°C - 105°C | 1.8V - 5.5V | 20 MHz | //! | ATtiny24A-MF | QFN_20 | QFN20 | -40°C - 125°C | 1.8V - 5.5V | 20 MHz | //! | ATtiny24A-MM8 | QFN_20 | VQFN20 | -40°C - 125°C | 1.8V - 5.5V | 20 MHz | //! | ATtiny24A-SSF | SOIC_14 | SOIC14 | -40°C - 125°C | 1.8V - 5.5V | 20 MHz | //! //! # Registers by module (not exhaustive) //! //! ## PORT modules //! //! * PORTA //! * PA0 (PA0) //! * PA1 (PA1) //! * PA2 (PA2) //! * PA3 (PA3) //! * PA4 (PA4) //! * PA5 (PA5) //! * PA6 (PA6) //! * PA7 (PA7) //! * PORTB //! * PB0 (PB0) //! * PB1 (PB1) //! * PB2 (PB2) //! * PB3 (PB3) //! //! ## ADC modules //! //! * ADC //! * PA0 (PA0) //! * PA1 (PA1) //! * PA2 (PA2) //! * PA3 (PA3) //! * PA4 (PA4) //! * PA5 (PA5) //! * PA6 (PA6) //! * PA7 (PA7) //! * PA0 (PA0) //! //! ## EEPROM modules //! //! * EEPROM pub const LOCKBIT: *mut u8 = 0x0 as *mut u8; pub const LOW: *mut u8 = 0x0 as *mut u8; pub const HIGH: *mut u8 = 0x1 as *mut u8; pub const EXTENDED: *mut u8 = 0x2 as *mut u8; /// Power Reduction Register. pub const PRR: *mut u8 = 0x20 as *mut u8; /// Digital Input Disable Register 0. pub const DIDR0: *mut u8 = 0x21 as *mut u8; /// ADC Control and Status Register B. pub const ADCSRB: *mut u8 = 0x23 as *mut u8; /// ADC Data Register Bytes. pub const ADC: *mut u16 = 0x24 as *mut u16; /// ADC Data Register Bytes low byte. pub const ADCL: *mut u8 = 0x24 as *mut u8; /// ADC Data Register Bytes high byte. pub const ADCH: *mut u8 = 0x25 as *mut u8; /// ADC Control and Status Register A. pub const ADCSRA: *mut u8 = 0x26 as *mut u8; /// ADC Multiplexer Selection Register. pub const ADMUX: *mut u8 = 0x27 as *mut u8; /// Analog Comparator Control And Status Register. pub const ACSR: *mut u8 = 0x28 as *mut u8; /// Timer/Counter Interrupt Flag register. pub const TIFR1: *mut u8 = 0x2B as *mut u8; /// Timer/Counter1 Interrupt Mask Register. pub const TIMSK1: *mut u8 = 0x2C as *mut u8; /// USI Control Register. pub const USICR: *mut u8 = 0x2D as *mut u8; /// USI Status Register. pub const USISR: *mut u8 = 0x2E as *mut u8; /// USI Data Register. pub const USIDR: *mut u8 = 0x2F as *mut u8; /// USI Buffer Register. pub const USIBR: *mut u8 = 0x30 as *mut u8; /// Pin Change Enable Mask 0. pub const PCMSK0: *mut u8 = 0x32 as *mut u8; /// General Purpose I/O Register 0. pub const GPIOR0: *mut u8 = 0x33 as *mut u8; /// General Purpose I/O Register 1. pub const GPIOR1: *mut u8 = 0x34 as *mut u8; /// General Purpose I/O Register 2. pub const GPIOR2: *mut u8 = 0x35 as *mut u8; /// Input Pins, Port B. pub const PINB: *mut u8 = 0x36 as *mut u8; /// Data Direction Register, Port B. pub const DDRB: *mut u8 = 0x37 as *mut u8; /// Data Register, Port B. pub const PORTB: *mut u8 = 0x38 as *mut u8; /// Port A Input Pins. pub const PINA: *mut u8 = 0x39 as *mut u8; /// Port A Data Direction Register. pub const DDRA: *mut u8 = 0x3A as *mut u8; /// Port A Data Register. pub const PORTA: *mut u8 = 0x3B as *mut u8; /// EEPROM Control Register. pub const EECR: *mut u8 = 0x3C as *mut u8; /// EEPROM Data Register. pub const EEDR: *mut u8 = 0x3D as *mut u8; /// EEPROM Address Register Bytes low byte. pub const EEARL: *mut u8 = 0x3E as *mut u8; /// EEPROM Address Register Bytes. pub const EEAR: *mut u16 = 0x3E as *mut u16; /// EEPROM Address Register Bytes high byte. pub const EEARH: *mut u8 = 0x3F as *mut u8; /// Pin Change Enable Mask 1. pub const PCMSK1: *mut u8 = 0x40 as *mut u8; /// Watchdog Timer Control Register. pub const WDTCSR: *mut u8 = 0x41 as *mut u8; /// Timer/Counter1 Control Register C. pub const TCCR1C: *mut u8 = 0x42 as *mut u8; /// General Timer/Counter Control Register. pub const GTCCR: *mut u8 = 0x43 as *mut u8; /// Timer/Counter1 Input Capture Register Bytes low byte. pub const ICR1L: *mut u8 = 0x44 as *mut u8; /// Timer/Counter1 Input Capture Register Bytes. pub const ICR1: *mut u16 = 0x44 as *mut u16; /// Timer/Counter1 Input Capture Register Bytes high byte. pub const ICR1H: *mut u8 = 0x45 as *mut u8; /// Clock Prescale Register. pub const CLKPR: *mut u8 = 0x46 as *mut u8; /// Timer/Counter1 Output Compare Register B Bytes. pub const OCR1B: *mut u16 = 0x48 as *mut u16; /// Timer/Counter1 Output Compare Register B Bytes low byte. pub const OCR1BL: *mut u8 = 0x48 as *mut u8; /// Timer/Counter1 Output Compare Register B Bytes high byte. pub const OCR1BH: *mut u8 = 0x49 as *mut u8; /// Timer/Counter1 Output Compare Register A Bytes. pub const OCR1A: *mut u16 = 0x4A as *mut u16; /// Timer/Counter1 Output Compare Register A Bytes low byte. pub const OCR1AL: *mut u8 = 0x4A as *mut u8; /// Timer/Counter1 Output Compare Register A Bytes high byte. pub const OCR1AH: *mut u8 = 0x4B as *mut u8; /// Timer/Counter1 Bytes. pub const TCNT1: *mut u16 = 0x4C as *mut u16; /// Timer/Counter1 Bytes low byte. pub const TCNT1L: *mut u8 = 0x4C as *mut u8; /// Timer/Counter1 Bytes high byte. pub const TCNT1H: *mut u8 = 0x4D as *mut u8; /// Timer/Counter1 Control Register B. pub const TCCR1B: *mut u8 = 0x4E as *mut u8; /// Timer/Counter1 Control Register A. pub const TCCR1A: *mut u8 = 0x4F as *mut u8; /// Timer/Counter Control Register A. pub const TCCR0A: *mut u8 = 0x50 as *mut u8; /// Oscillator Calibration Value. pub const OSCCAL: *mut u8 = 0x51 as *mut u8; /// Timer/Counter0. pub const TCNT0: *mut u8 = 0x52 as *mut u8; /// Timer/Counter Control Register B. pub const TCCR0B: *mut u8 = 0x53 as *mut u8; /// MCU Status Register. pub const MCUSR: *mut u8 = 0x54 as *mut u8; /// MCU Control Register. pub const MCUCR: *mut u8 = 0x55 as *mut u8; /// Timer/Counter0 Output Compare Register A. pub const OCR0A: *mut u8 = 0x56 as *mut u8; /// Store Program Memory Control Register. pub const SPMCSR: *mut u8 = 0x57 as *mut u8; /// Timer/Counter0 Interrupt Flag Register. pub const TIFR0: *mut u8 = 0x58 as *mut u8; /// Timer/Counter Interrupt Mask Register. pub const TIMSK0: *mut u8 = 0x59 as *mut u8; /// General Interrupt Flag register. pub const GIFR: *mut u8 = 0x5A as *mut u8; /// General Interrupt Mask Register. pub const GIMSK: *mut u8 = 0x5B as *mut u8; /// Timer/Counter0 Output Compare Register B. pub const OCR0B: *mut u8 = 0x5C as *mut u8; /// Stack Pointer Low. pub const SPL: *mut u8 = 0x5D as *mut u8; /// Status Register. pub const SREG: *mut u8 = 0x5F as *mut u8;