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//! The AVR ATtiny2313 microcontroller
//!
//! # Variants
//! |        | Pinout | Package | Operating temperature | Operating voltage | Max speed |
//! |--------|--------|---------|-----------------------|-------------------|-----------|
//! | standard |  |  | 0°C - 0°C | 1.8V - 5.5V | 0 MHz |
//!
//! # Registers by module (not exhaustive)
//!
//! ## PORT modules
//!
//! * PORTB
//! * PORTD
//! * PORTA
//!
//! ## USART modules
//!
//! * USART
//!
//! ## EEPROM modules
//!
//! * EEPROM

pub const LOW: *mut u8 = 0x0 as *mut u8;
pub const LOCKBIT: *mut u8 = 0x0 as *mut u8;
pub const HIGH: *mut u8 = 0x1 as *mut u8;
pub const EXTENDED: *mut u8 = 0x2 as *mut u8;
/// Digital Input Disable Register 1.
pub const DIDR: *mut u8 = 0x21 as *mut u8;
/// USART Baud Rate Register High Byte.
pub const UBRRH: *mut u8 = 0x22 as *mut u8;
/// USART Control and Status Register C.
pub const UCSRC: *mut u8 = 0x23 as *mut u8;
/// Analog Comparator Control And Status Register.
pub const ACSR: *mut u8 = 0x28 as *mut u8;
/// USART Baud Rate Register Low Byte.
pub const UBRRL: *mut u8 = 0x29 as *mut u8;
/// USART Control and Status Register B.
pub const UCSRB: *mut u8 = 0x2A as *mut u8;
/// USART Control and Status Register A.
pub const UCSRA: *mut u8 = 0x2B as *mut u8;
/// USART I/O Data Register.
pub const UDR: *mut u8 = 0x2C as *mut u8;
/// USI Control Register.
pub const USICR: *mut u8 = 0x2D as *mut u8;
/// USI Status Register.
pub const USISR: *mut u8 = 0x2E as *mut u8;
/// USI Data Register.
pub const USIDR: *mut u8 = 0x2F as *mut u8;
/// Input Pins, Port D.
pub const PIND: *mut u8 = 0x30 as *mut u8;
/// Data Direction Register, Port D.
pub const DDRD: *mut u8 = 0x31 as *mut u8;
/// Data Register, Port D.
pub const PORTD: *mut u8 = 0x32 as *mut u8;
/// General Purpose I/O Register 0.
pub const GPIOR0: *mut u8 = 0x33 as *mut u8;
/// General Purpose I/O Register 1.
pub const GPIOR1: *mut u8 = 0x34 as *mut u8;
/// General Purpose I/O Register 2.
pub const GPIOR2: *mut u8 = 0x35 as *mut u8;
/// Port B Input Pins.
pub const PINB: *mut u8 = 0x36 as *mut u8;
/// Port B Data Direction Register.
pub const DDRB: *mut u8 = 0x37 as *mut u8;
/// Port B Data Register.
pub const PORTB: *mut u8 = 0x38 as *mut u8;
/// Port A Input Pins.
pub const PINA: *mut u8 = 0x39 as *mut u8;
/// Port A Data Direction Register.
pub const DDRA: *mut u8 = 0x3A as *mut u8;
/// Port A Data Register.
pub const PORTA: *mut u8 = 0x3B as *mut u8;
/// EEPROM Control Register.
pub const EECR: *mut u8 = 0x3C as *mut u8;
/// EEPROM Data Register.
pub const EEDR: *mut u8 = 0x3D as *mut u8;
/// EEPROM Read/Write Access.
pub const EEAR: *mut u8 = 0x3E as *mut u8;
/// Pin-Change Mask register.
pub const PCMSK: *mut u8 = 0x40 as *mut u8;
/// Watchdog Timer Control Register.
pub const WDTCR: *mut u8 = 0x41 as *mut u8;
/// Timer/Counter1 Control Register C.
pub const TCCR1C: *mut u8 = 0x42 as *mut u8;
/// General Timer Counter Control Register.
pub const GTCCR: *mut u8 = 0x43 as *mut u8;
/// Timer/Counter1 Input Capture Register  Bytes.
pub const ICR1: *mut u16 = 0x44 as *mut u16;
/// Timer/Counter1 Input Capture Register  Bytes low byte.
pub const ICR1L: *mut u8 = 0x44 as *mut u8;
/// Timer/Counter1 Input Capture Register  Bytes high byte.
pub const ICR1H: *mut u8 = 0x45 as *mut u8;
/// Clock Prescale Register.
pub const CLKPR: *mut u8 = 0x46 as *mut u8;
/// Timer/Counter1 Output Compare Register  Bytes.
pub const OCR1B: *mut u16 = 0x48 as *mut u16;
/// Timer/Counter1 Output Compare Register  Bytes low byte.
pub const OCR1BL: *mut u8 = 0x48 as *mut u8;
/// Timer/Counter1 Output Compare Register  Bytes high byte.
pub const OCR1BH: *mut u8 = 0x49 as *mut u8;
/// Timer/Counter1 Output Compare Register  Bytes low byte.
pub const OCR1AL: *mut u8 = 0x4A as *mut u8;
/// Timer/Counter1 Output Compare Register  Bytes.
pub const OCR1A: *mut u16 = 0x4A as *mut u16;
/// Timer/Counter1 Output Compare Register  Bytes high byte.
pub const OCR1AH: *mut u8 = 0x4B as *mut u8;
/// Timer/Counter1  Bytes low byte.
pub const TCNT1L: *mut u8 = 0x4C as *mut u8;
/// Timer/Counter1  Bytes.
pub const TCNT1: *mut u16 = 0x4C as *mut u16;
/// Timer/Counter1  Bytes high byte.
pub const TCNT1H: *mut u8 = 0x4D as *mut u8;
/// Timer/Counter1 Control Register B.
pub const TCCR1B: *mut u8 = 0x4E as *mut u8;
/// Timer/Counter1 Control Register A.
pub const TCCR1A: *mut u8 = 0x4F as *mut u8;
/// Timer/Counter  Control Register A.
pub const TCCR0A: *mut u8 = 0x50 as *mut u8;
/// Oscillator Calibration Register.
pub const OSCCAL: *mut u8 = 0x51 as *mut u8;
/// Timer/Counter0.
pub const TCNT0: *mut u8 = 0x52 as *mut u8;
/// Timer/Counter Control Register B.
pub const TCCR0B: *mut u8 = 0x53 as *mut u8;
/// MCU Status register.
pub const MCUSR: *mut u8 = 0x54 as *mut u8;
/// MCU Control Register.
pub const MCUCR: *mut u8 = 0x55 as *mut u8;
/// Timer/Counter0 Output Compare Register.
pub const OCR0A: *mut u8 = 0x56 as *mut u8;
/// Store Program Memory Control and Status register.
pub const SPMCSR: *mut u8 = 0x57 as *mut u8;
/// Timer/Counter Interrupt Flag register.
pub const TIFR: *mut u8 = 0x58 as *mut u8;
/// Timer/Counter Interrupt Mask Register.
pub const TIMSK: *mut u8 = 0x59 as *mut u8;
/// Extended Interrupt Flag Register.
pub const EIFR: *mut u8 = 0x5A as *mut u8;
/// General Interrupt Mask Register.
pub const GIMSK: *mut u8 = 0x5B as *mut u8;
/// Timer/Counter0 Output Compare Register.
pub const OCR0B: *mut u8 = 0x5C as *mut u8;
/// Stack Pointer Low Byte.
pub const SPL: *mut u8 = 0x5D as *mut u8;
/// Status Register.
pub const SREG: *mut u8 = 0x5F as *mut u8;