//! The AVR ATmega2564RFR2 microcontroller
//!
//! # Variants
//! |        | Pinout | Package | Operating temperature | Operating voltage | Max speed |
//! |--------|--------|---------|-----------------------|-------------------|-----------|
//! | standard |  |  | 0°C - 0°C | 1.8V - 3.6V | 0 MHz |
//!
//! # Registers by module (not exhaustive)
//!
//! ## PORT modules
//!
//! * PORTA
//! * PORTB
//! * PORTC
//! * PORTD
//! * PORTE
//! * PORTF
//! * PORTG
//!
//! ## USART modules
//!
//! * USART0
//! * USART1
//!
//! ## EEPROM modules
//!
//! * EEPROM
//!
//! ## JTAG modules
//!
//! * JTAG
//!
//! ## ADC modules
//!
//! * ADC
//!
//! ## FLASH modules
//!
//! * FLASH

pub const LOCKBIT: *mut u8 = 0x0 as *mut u8;
pub const LOW: *mut u8 = 0x0 as *mut u8;
pub const HIGH: *mut u8 = 0x1 as *mut u8;
pub const EXTENDED: *mut u8 = 0x2 as *mut u8;
/// Port A Input Pins Address.
pub const PINA: *mut u8 = 0x20 as *mut u8;
/// Port A Data Direction Register.
pub const DDRA: *mut u8 = 0x21 as *mut u8;
/// Port A Data Register.
pub const PORTA: *mut u8 = 0x22 as *mut u8;
/// Port B Input Pins Address.
pub const PINB: *mut u8 = 0x23 as *mut u8;
/// Port B Data Direction Register.
pub const DDRB: *mut u8 = 0x24 as *mut u8;
/// Port B Data Register.
pub const PORTB: *mut u8 = 0x25 as *mut u8;
/// Port C Input Pins Address.
pub const PINC: *mut u8 = 0x26 as *mut u8;
/// Port C Data Direction Register.
pub const DDRC: *mut u8 = 0x27 as *mut u8;
/// Port C Data Register.
pub const PORTC: *mut u8 = 0x28 as *mut u8;
/// Port D Input Pins Address.
pub const PIND: *mut u8 = 0x29 as *mut u8;
/// Port D Data Direction Register.
pub const DDRD: *mut u8 = 0x2A as *mut u8;
/// Port D Data Register.
pub const PORTD: *mut u8 = 0x2B as *mut u8;
/// Port E Input Pins Address.
pub const PINE: *mut u8 = 0x2C as *mut u8;
/// Port E Data Direction Register.
pub const DDRE: *mut u8 = 0x2D as *mut u8;
/// Port E Data Register.
pub const PORTE: *mut u8 = 0x2E as *mut u8;
/// Port F Input Pins Address.
pub const PINF: *mut u8 = 0x2F as *mut u8;
/// Port F Data Direction Register.
pub const DDRF: *mut u8 = 0x30 as *mut u8;
/// Port F Data Register.
pub const PORTF: *mut u8 = 0x31 as *mut u8;
/// Port G Input Pins Address.
pub const PING: *mut u8 = 0x32 as *mut u8;
/// Port G Data Direction Register.
pub const DDRG: *mut u8 = 0x33 as *mut u8;
/// Port G Data Register.
pub const PORTG: *mut u8 = 0x34 as *mut u8;
/// Timer/Counter0 Interrupt Flag Register.
pub const TIFR0: *mut u8 = 0x35 as *mut u8;
/// Timer/Counter1 Interrupt Flag Register.
pub const TIFR1: *mut u8 = 0x36 as *mut u8;
/// Timer/Counter Interrupt Flag Register.
pub const TIFR2: *mut u8 = 0x37 as *mut u8;
/// Timer/Counter3 Interrupt Flag Register.
pub const TIFR3: *mut u8 = 0x38 as *mut u8;
/// Timer/Counter4 Interrupt Flag Register.
pub const TIFR4: *mut u8 = 0x39 as *mut u8;
/// Timer/Counter5 Interrupt Flag Register.
pub const TIFR5: *mut u8 = 0x3A as *mut u8;
/// Pin Change Interrupt Flag Register.
pub const PCIFR: *mut u8 = 0x3B as *mut u8;
/// External Interrupt Flag Register.
pub const EIFR: *mut u8 = 0x3C as *mut u8;
/// External Interrupt Mask Register.
pub const EIMSK: *mut u8 = 0x3D as *mut u8;
/// General Purpose IO Register 0.
pub const GPIOR0: *mut u8 = 0x3E as *mut u8;
/// EEPROM Control Register.
pub const EECR: *mut u8 = 0x3F as *mut u8;
/// EEPROM Data Register.
pub const EEDR: *mut u8 = 0x40 as *mut u8;
/// EEPROM Address Register  Bytes.
pub const EEAR: *mut u16 = 0x41 as *mut u16;
/// EEPROM Address Register  Bytes low byte.
pub const EEARL: *mut u8 = 0x41 as *mut u8;
/// EEPROM Address Register  Bytes high byte.
pub const EEARH: *mut u8 = 0x42 as *mut u8;
/// General Timer Counter Control register.
pub const GTCCR: *mut u8 = 0x43 as *mut u8;
/// Timer/Counter0 Control Register A.
pub const TCCR0A: *mut u8 = 0x44 as *mut u8;
/// Timer/Counter0 Control Register B.
pub const TCCR0B: *mut u8 = 0x45 as *mut u8;
/// Timer/Counter0 Register.
pub const TCNT0: *mut u8 = 0x46 as *mut u8;
/// Timer/Counter0 Output Compare Register.
pub const OCR0A: *mut u8 = 0x47 as *mut u8;
/// Timer/Counter0 Output Compare Register B.
pub const OCR0B: *mut u8 = 0x48 as *mut u8;
/// General Purpose IO Register 1.
pub const GPIOR1: *mut u8 = 0x4A as *mut u8;
/// General Purpose I/O Register 2.
pub const GPIOR2: *mut u8 = 0x4B as *mut u8;
/// SPI Control Register.
pub const SPCR: *mut u8 = 0x4C as *mut u8;
/// SPI Status Register.
pub const SPSR: *mut u8 = 0x4D as *mut u8;
/// SPI Data Register.
pub const SPDR: *mut u8 = 0x4E as *mut u8;
/// Analog Comparator Control And Status Register.
pub const ACSR: *mut u8 = 0x50 as *mut u8;
/// On-Chip Debug Register.
pub const OCDR: *mut u8 = 0x51 as *mut u8;
/// Sleep Mode Control Register.
pub const SMCR: *mut u8 = 0x53 as *mut u8;
/// MCU Status Register.
pub const MCUSR: *mut u8 = 0x54 as *mut u8;
/// MCU Control Register.
pub const MCUCR: *mut u8 = 0x55 as *mut u8;
/// Store Program Memory Control Register.
pub const SPMCSR: *mut u8 = 0x57 as *mut u8;
/// Extended Z-pointer Register for ELPM/SPM.
pub const RAMPZ: *mut u8 = 0x5B as *mut u8;
/// Extended Indirect Register.
pub const EIND: *mut u8 = 0x5C as *mut u8;
/// Stack Pointer.
pub const SP: *mut u16 = 0x5D as *mut u16;
/// Stack Pointer  low byte.
pub const SPL: *mut u8 = 0x5D as *mut u8;
/// Stack Pointer  high byte.
pub const SPH: *mut u8 = 0x5E as *mut u8;
/// Status Register.
pub const SREG: *mut u8 = 0x5F as *mut u8;
/// Watchdog Timer Control Register.
pub const WDTCSR: *mut u8 = 0x60 as *mut u8;
/// Clock Prescale Register.
pub const CLKPR: *mut u8 = 0x61 as *mut u8;
/// Power Reduction Register 2.
pub const PRR2: *mut u8 = 0x63 as *mut u8;
/// Power Reduction Register0.
pub const PRR0: *mut u8 = 0x64 as *mut u8;
/// Power Reduction Register 1.
pub const PRR1: *mut u8 = 0x65 as *mut u8;
/// Oscillator Calibration Value.
pub const OSCCAL: *mut u8 = 0x66 as *mut u8;
/// Reference Voltage Calibration Register.
pub const BGCR: *mut u8 = 0x67 as *mut u8;
/// Pin Change Interrupt Control Register.
pub const PCICR: *mut u8 = 0x68 as *mut u8;
/// External Interrupt Control Register A.
pub const EICRA: *mut u8 = 0x69 as *mut u8;
/// External Interrupt Control Register B.
pub const EICRB: *mut u8 = 0x6A as *mut u8;
/// Pin Change Mask Register 0.
pub const PCMSK0: *mut u8 = 0x6B as *mut u8;
/// Pin Change Mask Register 1.
pub const PCMSK1: *mut u8 = 0x6C as *mut u8;
/// Pin Change Mask Register 2.
pub const PCMSK2: *mut u8 = 0x6D as *mut u8;
/// Timer/Counter0 Interrupt Mask Register.
pub const TIMSK0: *mut u8 = 0x6E as *mut u8;
/// Timer/Counter1 Interrupt Mask Register.
pub const TIMSK1: *mut u8 = 0x6F as *mut u8;
/// Timer/Counter Interrupt Mask register.
pub const TIMSK2: *mut u8 = 0x70 as *mut u8;
/// Timer/Counter3 Interrupt Mask Register.
pub const TIMSK3: *mut u8 = 0x71 as *mut u8;
/// Timer/Counter4 Interrupt Mask Register.
pub const TIMSK4: *mut u8 = 0x72 as *mut u8;
/// Timer/Counter5 Interrupt Mask Register.
pub const TIMSK5: *mut u8 = 0x73 as *mut u8;
/// Flash Extended-Mode Control-Register.
pub const NEMCR: *mut u8 = 0x75 as *mut u8;
/// The ADC Control and Status Register C.
pub const ADCSRC: *mut u8 = 0x77 as *mut u8;
/// ADC Data Register  Bytes low byte.
pub const ADCL: *mut u8 = 0x78 as *mut u8;
/// ADC Data Register  Bytes.
pub const ADC: *mut u16 = 0x78 as *mut u16;
/// ADC Data Register  Bytes high byte.
pub const ADCH: *mut u8 = 0x79 as *mut u8;
/// The ADC Control and Status Register A.
pub const ADCSRA: *mut u8 = 0x7A as *mut u8;
/// The ADC Control and Status Register B.
pub const ADCSRB: *mut u8 = 0x7B as *mut u8;
/// The ADC Multiplexer Selection Register.
pub const ADMUX: *mut u8 = 0x7C as *mut u8;
/// Digital Input Disable Register 2.
pub const DIDR2: *mut u8 = 0x7D as *mut u8;
/// Digital Input Disable Register 0.
pub const DIDR0: *mut u8 = 0x7E as *mut u8;
/// Digital Input Disable Register 1.
pub const DIDR1: *mut u8 = 0x7F as *mut u8;
/// Timer/Counter1 Control Register A.
pub const TCCR1A: *mut u8 = 0x80 as *mut u8;
/// Timer/Counter1 Control Register B.
pub const TCCR1B: *mut u8 = 0x81 as *mut u8;
/// Timer/Counter1 Control Register C.
pub const TCCR1C: *mut u8 = 0x82 as *mut u8;
/// Timer/Counter1  Bytes.
pub const TCNT1: *mut u16 = 0x84 as *mut u16;
/// Timer/Counter1  Bytes low byte.
pub const TCNT1L: *mut u8 = 0x84 as *mut u8;
/// Timer/Counter1  Bytes high byte.
pub const TCNT1H: *mut u8 = 0x85 as *mut u8;
/// Timer/Counter1 Input Capture Register  Bytes.
pub const ICR1: *mut u16 = 0x86 as *mut u16;
/// Timer/Counter1 Input Capture Register  Bytes low byte.
pub const ICR1L: *mut u8 = 0x86 as *mut u8;
/// Timer/Counter1 Input Capture Register  Bytes high byte.
pub const ICR1H: *mut u8 = 0x87 as *mut u8;
/// Timer/Counter1 Output Compare Register A  Bytes low byte.
pub const OCR1AL: *mut u8 = 0x88 as *mut u8;
/// Timer/Counter1 Output Compare Register A  Bytes.
pub const OCR1A: *mut u16 = 0x88 as *mut u16;
/// Timer/Counter1 Output Compare Register A  Bytes high byte.
pub const OCR1AH: *mut u8 = 0x89 as *mut u8;
/// Timer/Counter1 Output Compare Register B  Bytes.
pub const OCR1B: *mut u16 = 0x8A as *mut u16;
/// Timer/Counter1 Output Compare Register B  Bytes low byte.
pub const OCR1BL: *mut u8 = 0x8A as *mut u8;
/// Timer/Counter1 Output Compare Register B  Bytes high byte.
pub const OCR1BH: *mut u8 = 0x8B as *mut u8;
/// Timer/Counter1 Output Compare Register C  Bytes.
pub const OCR1C: *mut u16 = 0x8C as *mut u16;
/// Timer/Counter1 Output Compare Register C  Bytes low byte.
pub const OCR1CL: *mut u8 = 0x8C as *mut u8;
/// Timer/Counter1 Output Compare Register C  Bytes high byte.
pub const OCR1CH: *mut u8 = 0x8D as *mut u8;
/// Timer/Counter3 Control Register A.
pub const TCCR3A: *mut u8 = 0x90 as *mut u8;
/// Timer/Counter3 Control Register B.
pub const TCCR3B: *mut u8 = 0x91 as *mut u8;
/// Timer/Counter3 Control Register C.
pub const TCCR3C: *mut u8 = 0x92 as *mut u8;
/// Timer/Counter3  Bytes low byte.
pub const TCNT3L: *mut u8 = 0x94 as *mut u8;
/// Timer/Counter3  Bytes.
pub const TCNT3: *mut u16 = 0x94 as *mut u16;
/// Timer/Counter3  Bytes high byte.
pub const TCNT3H: *mut u8 = 0x95 as *mut u8;
/// Timer/Counter3 Input Capture Register  Bytes.
pub const ICR3: *mut u16 = 0x96 as *mut u16;
/// Timer/Counter3 Input Capture Register  Bytes low byte.
pub const ICR3L: *mut u8 = 0x96 as *mut u8;
/// Timer/Counter3 Input Capture Register  Bytes high byte.
pub const ICR3H: *mut u8 = 0x97 as *mut u8;
/// Timer/Counter3 Output Compare Register A  Bytes.
pub const OCR3A: *mut u16 = 0x98 as *mut u16;
/// Timer/Counter3 Output Compare Register A  Bytes low byte.
pub const OCR3AL: *mut u8 = 0x98 as *mut u8;
/// Timer/Counter3 Output Compare Register A  Bytes high byte.
pub const OCR3AH: *mut u8 = 0x99 as *mut u8;
/// Timer/Counter3 Output Compare Register B  Bytes low byte.
pub const OCR3BL: *mut u8 = 0x9A as *mut u8;
/// Timer/Counter3 Output Compare Register B  Bytes.
pub const OCR3B: *mut u16 = 0x9A as *mut u16;
/// Timer/Counter3 Output Compare Register B  Bytes high byte.
pub const OCR3BH: *mut u8 = 0x9B as *mut u8;
/// Timer/Counter3 Output Compare Register C  Bytes low byte.
pub const OCR3CL: *mut u8 = 0x9C as *mut u8;
/// Timer/Counter3 Output Compare Register C  Bytes.
pub const OCR3C: *mut u16 = 0x9C as *mut u16;
/// Timer/Counter3 Output Compare Register C  Bytes high byte.
pub const OCR3CH: *mut u8 = 0x9D as *mut u8;
/// Timer/Counter4 Control Register A.
pub const TCCR4A: *mut u8 = 0xA0 as *mut u8;
/// Timer/Counter4 Control Register B.
pub const TCCR4B: *mut u8 = 0xA1 as *mut u8;
/// Timer/Counter4 Control Register C.
pub const TCCR4C: *mut u8 = 0xA2 as *mut u8;
/// Timer/Counter4  Bytes low byte.
pub const TCNT4L: *mut u8 = 0xA4 as *mut u8;
/// Timer/Counter4  Bytes.
pub const TCNT4: *mut u16 = 0xA4 as *mut u16;
/// Timer/Counter4  Bytes high byte.
pub const TCNT4H: *mut u8 = 0xA5 as *mut u8;
/// Timer/Counter4 Input Capture Register  Bytes low byte.
pub const ICR4L: *mut u8 = 0xA6 as *mut u8;
/// Timer/Counter4 Input Capture Register  Bytes.
pub const ICR4: *mut u16 = 0xA6 as *mut u16;
/// Timer/Counter4 Input Capture Register  Bytes high byte.
pub const ICR4H: *mut u8 = 0xA7 as *mut u8;
/// Timer/Counter4 Output Compare Register A  Bytes low byte.
pub const OCR4AL: *mut u8 = 0xA8 as *mut u8;
/// Timer/Counter4 Output Compare Register A  Bytes.
pub const OCR4A: *mut u16 = 0xA8 as *mut u16;
/// Timer/Counter4 Output Compare Register A  Bytes high byte.
pub const OCR4AH: *mut u8 = 0xA9 as *mut u8;
/// Timer/Counter4 Output Compare Register B  Bytes.
pub const OCR4B: *mut u16 = 0xAA as *mut u16;
/// Timer/Counter4 Output Compare Register B  Bytes low byte.
pub const OCR4BL: *mut u8 = 0xAA as *mut u8;
/// Timer/Counter4 Output Compare Register B  Bytes high byte.
pub const OCR4BH: *mut u8 = 0xAB as *mut u8;
/// Timer/Counter4 Output Compare Register C  Bytes.
pub const OCR4C: *mut u16 = 0xAC as *mut u16;
/// Timer/Counter4 Output Compare Register C  Bytes low byte.
pub const OCR4CL: *mut u8 = 0xAC as *mut u8;
/// Timer/Counter4 Output Compare Register C  Bytes high byte.
pub const OCR4CH: *mut u8 = 0xAD as *mut u8;
/// Timer/Counter2 Control Register A.
pub const TCCR2A: *mut u8 = 0xB0 as *mut u8;
/// Timer/Counter2 Control Register B.
pub const TCCR2B: *mut u8 = 0xB1 as *mut u8;
/// Timer/Counter2.
pub const TCNT2: *mut u8 = 0xB2 as *mut u8;
/// Timer/Counter2 Output Compare Register A.
pub const OCR2A: *mut u8 = 0xB3 as *mut u8;
/// Timer/Counter2 Output Compare Register B.
pub const OCR2B: *mut u8 = 0xB4 as *mut u8;
/// Asynchronous Status Register.
pub const ASSR: *mut u8 = 0xB6 as *mut u8;
/// TWI Bit Rate Register.
pub const TWBR: *mut u8 = 0xB8 as *mut u8;
/// TWI Status Register.
pub const TWSR: *mut u8 = 0xB9 as *mut u8;
/// TWI (Slave) Address Register.
pub const TWAR: *mut u8 = 0xBA as *mut u8;
/// TWI Data Register.
pub const TWDR: *mut u8 = 0xBB as *mut u8;
/// TWI Control Register.
pub const TWCR: *mut u8 = 0xBC as *mut u8;
/// TWI (Slave) Address Mask Register.
pub const TWAMR: *mut u8 = 0xBD as *mut u8;
/// Transceiver Interrupt Enable Register 1.
pub const IRQ_MASK1: *mut u8 = 0xBE as *mut u8;
/// Transceiver Interrupt Status Register 1.
pub const IRQ_STATUS1: *mut u8 = 0xBF as *mut u8;
/// USART0 MSPIM Control and Status Register A.
pub const UCSR0A: *mut u8 = 0xC0 as *mut u8;
/// USART0 MSPIM Control and Status Register B.
pub const UCSR0B: *mut u8 = 0xC1 as *mut u8;
/// USART0 MSPIM Control and Status Register C.
pub const UCSR0C: *mut u8 = 0xC2 as *mut u8;
/// USART0 Baud Rate Register  Bytes.
pub const UBRR0: *mut u16 = 0xC4 as *mut u16;
/// USART0 Baud Rate Register  Bytes low byte.
pub const UBRR0L: *mut u8 = 0xC4 as *mut u8;
/// USART0 Baud Rate Register  Bytes high byte.
pub const UBRR0H: *mut u8 = 0xC5 as *mut u8;
/// USART0 I/O Data Register.
pub const UDR0: *mut u8 = 0xC6 as *mut u8;
/// USART1 MSPIM Control and Status Register A.
pub const UCSR1A: *mut u8 = 0xC8 as *mut u8;
/// USART1 MSPIM Control and Status Register B.
pub const UCSR1B: *mut u8 = 0xC9 as *mut u8;
/// USART1 MSPIM Control and Status Register C.
pub const UCSR1C: *mut u8 = 0xCA as *mut u8;
/// USART1 Baud Rate Register  Bytes.
pub const UBRR1: *mut u16 = 0xCC as *mut u16;
/// USART1 Baud Rate Register  Bytes low byte.
pub const UBRR1L: *mut u8 = 0xCC as *mut u8;
/// USART1 Baud Rate Register  Bytes high byte.
pub const UBRR1H: *mut u8 = 0xCD as *mut u8;
/// USART1 I/O Data Register.
pub const UDR1: *mut u8 = 0xCE as *mut u8;
/// Symbol Counter Received Frame Timestamp Register LL-Byte.
pub const SCRSTRLL: *mut u8 = 0xD7 as *mut u8;
/// Symbol Counter Received Frame Timestamp Register LH-Byte.
pub const SCRSTRLH: *mut u8 = 0xD8 as *mut u8;
/// Symbol Counter Received Frame Timestamp Register HL-Byte.
pub const SCRSTRHL: *mut u8 = 0xD9 as *mut u8;
/// Symbol Counter Received Frame Timestamp Register HH-Byte.
pub const SCRSTRHH: *mut u8 = 0xDA as *mut u8;
/// Symbol Counter Compare Source Register.
pub const SCCSR: *mut u8 = 0xDB as *mut u8;
/// Symbol Counter Control Register 0.
pub const SCCR0: *mut u8 = 0xDC as *mut u8;
/// Symbol Counter Control Register 1.
pub const SCCR1: *mut u8 = 0xDD as *mut u8;
/// Symbol Counter Status Register.
pub const SCSR: *mut u8 = 0xDE as *mut u8;
/// Symbol Counter Interrupt Mask Register.
pub const SCIRQM: *mut u8 = 0xDF as *mut u8;
/// Symbol Counter Interrupt Status Register.
pub const SCIRQS: *mut u8 = 0xE0 as *mut u8;
/// Symbol Counter Register LL-Byte.
pub const SCCNTLL: *mut u8 = 0xE1 as *mut u8;
/// Symbol Counter Register LH-Byte.
pub const SCCNTLH: *mut u8 = 0xE2 as *mut u8;
/// Symbol Counter Register HL-Byte.
pub const SCCNTHL: *mut u8 = 0xE3 as *mut u8;
/// Symbol Counter Register HH-Byte.
pub const SCCNTHH: *mut u8 = 0xE4 as *mut u8;
/// Symbol Counter Beacon Timestamp Register LL-Byte.
pub const SCBTSRLL: *mut u8 = 0xE5 as *mut u8;
/// Symbol Counter Beacon Timestamp Register LH-Byte.
pub const SCBTSRLH: *mut u8 = 0xE6 as *mut u8;
/// Symbol Counter Beacon Timestamp Register HL-Byte.
pub const SCBTSRHL: *mut u8 = 0xE7 as *mut u8;
/// Symbol Counter Beacon Timestamp Register HH-Byte.
pub const SCBTSRHH: *mut u8 = 0xE8 as *mut u8;
/// Symbol Counter Frame Timestamp Register LL-Byte.
pub const SCTSRLL: *mut u8 = 0xE9 as *mut u8;
/// Symbol Counter Frame Timestamp Register LH-Byte.
pub const SCTSRLH: *mut u8 = 0xEA as *mut u8;
/// Symbol Counter Frame Timestamp Register HL-Byte.
pub const SCTSRHL: *mut u8 = 0xEB as *mut u8;
/// Symbol Counter Frame Timestamp Register HH-Byte.
pub const SCTSRHH: *mut u8 = 0xEC as *mut u8;
/// Symbol Counter Output Compare Register 3 LL-Byte.
pub const SCOCR3LL: *mut u8 = 0xED as *mut u8;
/// Symbol Counter Output Compare Register 3 LH-Byte.
pub const SCOCR3LH: *mut u8 = 0xEE as *mut u8;
/// Symbol Counter Output Compare Register 3 HL-Byte.
pub const SCOCR3HL: *mut u8 = 0xEF as *mut u8;
/// Symbol Counter Output Compare Register 3 HH-Byte.
pub const SCOCR3HH: *mut u8 = 0xF0 as *mut u8;
/// Symbol Counter Output Compare Register 2 LL-Byte.
pub const SCOCR2LL: *mut u8 = 0xF1 as *mut u8;
/// Symbol Counter Output Compare Register 2 LH-Byte.
pub const SCOCR2LH: *mut u8 = 0xF2 as *mut u8;
/// Symbol Counter Output Compare Register 2 HL-Byte.
pub const SCOCR2HL: *mut u8 = 0xF3 as *mut u8;
/// Symbol Counter Output Compare Register 2 HH-Byte.
pub const SCOCR2HH: *mut u8 = 0xF4 as *mut u8;
/// Symbol Counter Output Compare Register 1 LL-Byte.
pub const SCOCR1LL: *mut u8 = 0xF5 as *mut u8;
/// Symbol Counter Output Compare Register 1 LH-Byte.
pub const SCOCR1LH: *mut u8 = 0xF6 as *mut u8;
/// Symbol Counter Output Compare Register 1 HL-Byte.
pub const SCOCR1HL: *mut u8 = 0xF7 as *mut u8;
/// Symbol Counter Output Compare Register 1 HH-Byte.
pub const SCOCR1HH: *mut u8 = 0xF8 as *mut u8;
/// Symbol Counter Transmit Frame Timestamp Register LL-Byte.
pub const SCTSTRLL: *mut u8 = 0xF9 as *mut u8;
/// Symbol Counter Transmit Frame Timestamp Register LH-Byte.
pub const SCTSTRLH: *mut u8 = 0xFA as *mut u8;
/// Symbol Counter Transmit Frame Timestamp Register HL-Byte.
pub const SCTSTRHL: *mut u8 = 0xFB as *mut u8;
/// Symbol Counter Transmit Frame Timestamp Register HH-Byte.
pub const SCTSTRHH: *mut u8 = 0xFC as *mut u8;
/// Multiple Address Filter Configuration Register 0.
pub const MAFCR0: *mut u8 = 0x10C as *mut u8;
/// Multiple Address Filter Configuration Register 1.
pub const MAFCR1: *mut u8 = 0x10D as *mut u8;
/// Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte).
pub const MAFSA0L: *mut u8 = 0x10E as *mut u8;
/// Transceiver MAC Short Address Register for Frame Filter 0 (High Byte).
pub const MAFSA0H: *mut u8 = 0x10F as *mut u8;
/// Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte).
pub const MAFPA0L: *mut u8 = 0x110 as *mut u8;
/// Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte).
pub const MAFPA0H: *mut u8 = 0x111 as *mut u8;
/// Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte).
pub const MAFSA1L: *mut u8 = 0x112 as *mut u8;
/// Transceiver MAC Short Address Register for Frame Filter 1 (High Byte).
pub const MAFSA1H: *mut u8 = 0x113 as *mut u8;
/// Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte).
pub const MAFPA1L: *mut u8 = 0x114 as *mut u8;
/// Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte).
pub const MAFPA1H: *mut u8 = 0x115 as *mut u8;
/// Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte).
pub const MAFSA2L: *mut u8 = 0x116 as *mut u8;
/// Transceiver MAC Short Address Register for Frame Filter 2 (High Byte).
pub const MAFSA2H: *mut u8 = 0x117 as *mut u8;
/// Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte).
pub const MAFPA2L: *mut u8 = 0x118 as *mut u8;
/// Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte).
pub const MAFPA2H: *mut u8 = 0x119 as *mut u8;
/// Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte).
pub const MAFSA3L: *mut u8 = 0x11A as *mut u8;
/// Transceiver MAC Short Address Register for Frame Filter 3 (High Byte).
pub const MAFSA3H: *mut u8 = 0x11B as *mut u8;
/// Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte).
pub const MAFPA3L: *mut u8 = 0x11C as *mut u8;
/// Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte).
pub const MAFPA3H: *mut u8 = 0x11D as *mut u8;
/// Timer/Counter5 Control Register A.
pub const TCCR5A: *mut u8 = 0x120 as *mut u8;
/// Timer/Counter5 Control Register B.
pub const TCCR5B: *mut u8 = 0x121 as *mut u8;
/// Timer/Counter5 Control Register C.
pub const TCCR5C: *mut u8 = 0x122 as *mut u8;
/// Timer/Counter5  Bytes low byte.
pub const TCNT5L: *mut u8 = 0x124 as *mut u8;
/// Timer/Counter5  Bytes.
pub const TCNT5: *mut u16 = 0x124 as *mut u16;
/// Timer/Counter5  Bytes high byte.
pub const TCNT5H: *mut u8 = 0x125 as *mut u8;
/// Timer/Counter5 Input Capture Register  Bytes low byte.
pub const ICR5L: *mut u8 = 0x126 as *mut u8;
/// Timer/Counter5 Input Capture Register  Bytes.
pub const ICR5: *mut u16 = 0x126 as *mut u16;
/// Timer/Counter5 Input Capture Register  Bytes high byte.
pub const ICR5H: *mut u8 = 0x127 as *mut u8;
/// Timer/Counter5 Output Compare Register A  Bytes.
pub const OCR5A: *mut u16 = 0x128 as *mut u16;
/// Timer/Counter5 Output Compare Register A  Bytes low byte.
pub const OCR5AL: *mut u8 = 0x128 as *mut u8;
/// Timer/Counter5 Output Compare Register A  Bytes high byte.
pub const OCR5AH: *mut u8 = 0x129 as *mut u8;
/// Timer/Counter5 Output Compare Register B  Bytes low byte.
pub const OCR5BL: *mut u8 = 0x12A as *mut u8;
/// Timer/Counter5 Output Compare Register B  Bytes.
pub const OCR5B: *mut u16 = 0x12A as *mut u16;
/// Timer/Counter5 Output Compare Register B  Bytes high byte.
pub const OCR5BH: *mut u8 = 0x12B as *mut u8;
/// Timer/Counter5 Output Compare Register C  Bytes.
pub const OCR5C: *mut u16 = 0x12C as *mut u16;
/// Timer/Counter5 Output Compare Register C  Bytes low byte.
pub const OCR5CL: *mut u8 = 0x12C as *mut u8;
/// Timer/Counter5 Output Compare Register C  Bytes high byte.
pub const OCR5CH: *mut u8 = 0x12D as *mut u8;
/// Low Leakage Voltage Regulator Control Register.
pub const LLCR: *mut u8 = 0x12F as *mut u8;
/// Low Leakage Voltage Regulator Data Register (Low-Byte).
pub const LLDRL: *mut u8 = 0x130 as *mut u8;
/// Low Leakage Voltage Regulator Data Register (High-Byte).
pub const LLDRH: *mut u8 = 0x131 as *mut u8;
/// Data Retention Configuration Register #3.
pub const DRTRAM3: *mut u8 = 0x132 as *mut u8;
/// Data Retention Configuration Register #2.
pub const DRTRAM2: *mut u8 = 0x133 as *mut u8;
/// Data Retention Configuration Register #1.
pub const DRTRAM1: *mut u8 = 0x134 as *mut u8;
/// Data Retention Configuration Register #0.
pub const DRTRAM0: *mut u8 = 0x135 as *mut u8;
/// Port Driver Strength Register 0.
pub const DPDS0: *mut u8 = 0x136 as *mut u8;
/// Port Driver Strength Register 1.
pub const DPDS1: *mut u8 = 0x137 as *mut u8;
/// Power Amplifier Ramp up/down Control Register.
pub const PARCR: *mut u8 = 0x138 as *mut u8;
/// Transceiver Pin Register.
pub const TRXPR: *mut u8 = 0x139 as *mut u8;
/// AES Control Register.
pub const AES_CTRL: *mut u8 = 0x13C as *mut u8;
/// AES Status Register.
pub const AES_STATUS: *mut u8 = 0x13D as *mut u8;
/// AES Plain and Cipher Text Buffer Register.
pub const AES_STATE: *mut u8 = 0x13E as *mut u8;
/// AES Encryption and Decryption Key Buffer Register.
pub const AES_KEY: *mut u8 = 0x13F as *mut u8;
/// Transceiver Status Register.
pub const TRX_STATUS: *mut u8 = 0x141 as *mut u8;
/// Transceiver State Control Register.
pub const TRX_STATE: *mut u8 = 0x142 as *mut u8;
/// Reserved.
pub const TRX_CTRL_0: *mut u8 = 0x143 as *mut u8;
/// Transceiver Control Register 1.
pub const TRX_CTRL_1: *mut u8 = 0x144 as *mut u8;
/// Transceiver Transmit Power Control Register.
pub const PHY_TX_PWR: *mut u8 = 0x145 as *mut u8;
/// Receiver Signal Strength Indicator Register.
pub const PHY_RSSI: *mut u8 = 0x146 as *mut u8;
/// Transceiver Energy Detection Level Register.
pub const PHY_ED_LEVEL: *mut u8 = 0x147 as *mut u8;
/// Transceiver Clear Channel Assessment (CCA) Control Register.
pub const PHY_CC_CCA: *mut u8 = 0x148 as *mut u8;
/// Transceiver CCA Threshold Setting Register.
pub const CCA_THRES: *mut u8 = 0x149 as *mut u8;
/// Transceiver Receive Control Register.
pub const RX_CTRL: *mut u8 = 0x14A as *mut u8;
/// Start of Frame Delimiter Value Register.
pub const SFD_VALUE: *mut u8 = 0x14B as *mut u8;
/// Transceiver Control Register 2.
pub const TRX_CTRL_2: *mut u8 = 0x14C as *mut u8;
/// Antenna Diversity Control Register.
pub const ANT_DIV: *mut u8 = 0x14D as *mut u8;
/// Transceiver Interrupt Enable Register.
pub const IRQ_MASK: *mut u8 = 0x14E as *mut u8;
/// Transceiver Interrupt Status Register.
pub const IRQ_STATUS: *mut u8 = 0x14F as *mut u8;
/// Voltage Regulator Control and Status Register.
pub const VREG_CTRL: *mut u8 = 0x150 as *mut u8;
/// Battery Monitor Control and Status Register.
pub const BATMON: *mut u8 = 0x151 as *mut u8;
/// Crystal Oscillator Control Register.
pub const XOSC_CTRL: *mut u8 = 0x152 as *mut u8;
/// Channel Control Register 0.
pub const CC_CTRL_0: *mut u8 = 0x153 as *mut u8;
/// Channel Control Register 1.
pub const CC_CTRL_1: *mut u8 = 0x154 as *mut u8;
/// Transceiver Receiver Sensitivity Control Register.
pub const RX_SYN: *mut u8 = 0x155 as *mut u8;
/// Transceiver Reduced Power Consumption Control.
pub const TRX_RPC: *mut u8 = 0x156 as *mut u8;
/// Transceiver Acknowledgment Frame Control Register 1.
pub const XAH_CTRL_1: *mut u8 = 0x157 as *mut u8;
/// Transceiver Filter Tuning Control Register.
pub const FTN_CTRL: *mut u8 = 0x158 as *mut u8;
/// Transceiver Center Frequency Calibration Control Register.
pub const PLL_CF: *mut u8 = 0x15A as *mut u8;
/// Transceiver Delay Cell Calibration Control Register.
pub const PLL_DCU: *mut u8 = 0x15B as *mut u8;
/// Device Identification Register (Part Number).
pub const PART_NUM: *mut u8 = 0x15C as *mut u8;
/// Device Identification Register (Version Number).
pub const VERSION_NUM: *mut u8 = 0x15D as *mut u8;
/// Device Identification Register (Manufacture ID Low Byte).
pub const MAN_ID_0: *mut u8 = 0x15E as *mut u8;
/// Device Identification Register (Manufacture ID High Byte).
pub const MAN_ID_1: *mut u8 = 0x15F as *mut u8;
/// Transceiver MAC Short Address Register (Low Byte).
pub const SHORT_ADDR_0: *mut u8 = 0x160 as *mut u8;
/// Transceiver MAC Short Address Register (High Byte).
pub const SHORT_ADDR_1: *mut u8 = 0x161 as *mut u8;
/// Transceiver Personal Area Network ID Register (Low Byte).
pub const PAN_ID_0: *mut u8 = 0x162 as *mut u8;
/// Transceiver Personal Area Network ID Register (High Byte).
pub const PAN_ID_1: *mut u8 = 0x163 as *mut u8;
/// Transceiver MAC IEEE Address Register 0.
pub const IEEE_ADDR_0: *mut u8 = 0x164 as *mut u8;
/// Transceiver MAC IEEE Address Register 1.
pub const IEEE_ADDR_1: *mut u8 = 0x165 as *mut u8;
/// Transceiver MAC IEEE Address Register 2.
pub const IEEE_ADDR_2: *mut u8 = 0x166 as *mut u8;
/// Transceiver MAC IEEE Address Register 3.
pub const IEEE_ADDR_3: *mut u8 = 0x167 as *mut u8;
/// Transceiver MAC IEEE Address Register 4.
pub const IEEE_ADDR_4: *mut u8 = 0x168 as *mut u8;
/// Transceiver MAC IEEE Address Register 5.
pub const IEEE_ADDR_5: *mut u8 = 0x169 as *mut u8;
/// Transceiver MAC IEEE Address Register 6.
pub const IEEE_ADDR_6: *mut u8 = 0x16A as *mut u8;
/// Transceiver MAC IEEE Address Register 7.
pub const IEEE_ADDR_7: *mut u8 = 0x16B as *mut u8;
/// Transceiver Extended Operating Mode Control Register.
pub const XAH_CTRL_0: *mut u8 = 0x16C as *mut u8;
/// Transceiver CSMA-CA Random Number Generator Seed Register.
pub const CSMA_SEED_0: *mut u8 = 0x16D as *mut u8;
/// Transceiver Acknowledgment Frame Control Register 2.
pub const CSMA_SEED_1: *mut u8 = 0x16E as *mut u8;
/// Transceiver CSMA-CA Back-off Exponent Control Register.
pub const CSMA_BE: *mut u8 = 0x16F as *mut u8;
/// Transceiver Digital Test Control Register.
pub const TST_CTRL_DIGI: *mut u8 = 0x176 as *mut u8;
/// Transceiver Received Frame Length Register.
pub const TST_RX_LENGTH: *mut u8 = 0x17B as *mut u8;
/// Start of frame buffer.
pub const TRXFBST: *mut u8 = 0x180 as *mut u8;
/// End of frame buffer.
pub const TRXFBEND: *mut u8 = 0x1FF as *mut u8;