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//! The AVR ATA6285 microcontroller
//!
//! # Variants
//! |        | Pinout | Package | Operating temperature | Operating voltage | Max speed |
//! |--------|--------|---------|-----------------------|-------------------|-----------|
//! | standard |  |  | 0°C - 0°C | 2V - 3.6V | 0 MHz |
//!
//! # Registers by module (not exhaustive)
//!
//! ## EEPROM modules
//!
//! * EEPROM

pub const LOW: *mut u8 = 0x0 as *mut u8;
pub const LOCKBIT: *mut u8 = 0x0 as *mut u8;
pub const HIGH: *mut u8 = 0x1 as *mut u8;
/// Port B Input Pins.
pub const PINB: *mut u8 = 0x23 as *mut u8;
/// Port B Data Direction Register.
pub const DDRB: *mut u8 = 0x24 as *mut u8;
/// Port B Data Register.
pub const PORTB: *mut u8 = 0x25 as *mut u8;
/// Port C Input Pins.
pub const PINC: *mut u8 = 0x26 as *mut u8;
/// Port C Data Direction Register.
pub const DDRC: *mut u8 = 0x27 as *mut u8;
/// Port C Data Register.
pub const PORTC: *mut u8 = 0x28 as *mut u8;
/// Port D Input Pins.
pub const PIND: *mut u8 = 0x29 as *mut u8;
/// Port D Data Direction Register.
pub const DDRD: *mut u8 = 0x2A as *mut u8;
/// Port D Data Register.
pub const PORTD: *mut u8 = 0x2B as *mut u8;
/// Clock Management Control Register.
pub const CMCR: *mut u8 = 0x2F as *mut u8;
/// Clock Management Status Register.
pub const CMSR: *mut u8 = 0x30 as *mut u8;
/// Timer 2 Control Register A.
pub const T2CRA: *mut u8 = 0x31 as *mut u8;
/// Timer 2 Control Register B.
pub const T2CRB: *mut u8 = 0x32 as *mut u8;
/// Timer 3 Control Register A.
pub const T3CRA: *mut u8 = 0x34 as *mut u8;
/// Voltage Monitor Control and Status Register.
pub const VMCSR: *mut u8 = 0x36 as *mut u8;
/// Pin Change Interrupt Flag Register.
pub const PCIFR: *mut u8 = 0x37 as *mut u8;
/// Low Frequency Flag Register.
pub const LFFR: *mut u8 = 0x38 as *mut u8;
/// Sensor Status + Flag Register.
pub const SSFR: *mut u8 = 0x39 as *mut u8;
/// Timer1/0 Interrupt Flag Register.
pub const T10IFR: *mut u8 = 0x3A as *mut u8;
/// Timer2 Interrupt Flag Register.
pub const T2IFR: *mut u8 = 0x3B as *mut u8;
/// Timer3 Interrupt Flag Register.
pub const T3IFR: *mut u8 = 0x3C as *mut u8;
/// External Interrupt Flag Register.
pub const EIFR: *mut u8 = 0x3D as *mut u8;
/// General Purpose I/O Register 0.
pub const GPIOR0: *mut u8 = 0x3E as *mut u8;
/// EEPROM Control Register.
pub const EECR: *mut u8 = 0x3F as *mut u8;
/// EEPROM Data Register.
pub const EEDR: *mut u8 = 0x40 as *mut u8;
/// EEPROM Address Register  Bytes low byte.
pub const EEARL: *mut u8 = 0x41 as *mut u8;
/// EEPROM Address Register  Bytes.
pub const EEAR: *mut u16 = 0x41 as *mut u16;
/// EEPROM Address Register  Bytes high byte.
pub const EEARH: *mut u8 = 0x42 as *mut u8;
/// Pin Change Interrupt Control Register.
pub const PCICR: *mut u8 = 0x43 as *mut u8;
/// External Interrupt Mask Register.
pub const EIMSK: *mut u8 = 0x44 as *mut u8;
/// Sensor Voltage Control Register.
pub const SVCR: *mut u8 = 0x47 as *mut u8;
/// Sensor Control Register.
pub const SCR: *mut u8 = 0x48 as *mut u8;
/// Sensor Capacitor Control Register.
pub const SCCR: *mut u8 = 0x49 as *mut u8;
/// General Purpose I/O Register 1.
pub const GPIOR1: *mut u8 = 0x4A as *mut u8;
/// General Purpose I/O Register 2.
pub const GPIOR2: *mut u8 = 0x4B as *mut u8;
/// SPI Control Register.
pub const SPCR: *mut u8 = 0x4C as *mut u8;
/// SPI Status Register.
pub const SPSR: *mut u8 = 0x4D as *mut u8;
/// SPI Data Register.
pub const SPDR: *mut u8 = 0x4E as *mut u8;
/// Timer 2 Modulator Data Register.
pub const T2MDR: *mut u8 = 0x4F as *mut u8;
/// LF RSSI Data Register.
pub const LFRR: *mut u8 = 0x50 as *mut u8;
/// LF receiver Control und Data Register.
pub const LFCDR: *mut u8 = 0x52 as *mut u8;
/// Sleep Mode Control Register.
pub const SMCR: *mut u8 = 0x53 as *mut u8;
/// MCU Status Register.
pub const MCUSR: *mut u8 = 0x54 as *mut u8;
/// MCU Control Register.
pub const MCUCR: *mut u8 = 0x55 as *mut u8;
/// Low Frequency Receive data Buffer.
pub const LFRB: *mut u8 = 0x56 as *mut u8;
/// Store Program Memory Control Register.
pub const SPMCSR: *mut u8 = 0x57 as *mut u8;
/// Timer 1 Control Register.
pub const T1CR: *mut u8 = 0x58 as *mut u8;
/// Timer 0 Control Register.
pub const T0CR: *mut u8 = 0x59 as *mut u8;
/// Clock Management Interrupt Mask Register.
pub const CMIMR: *mut u8 = 0x5B as *mut u8;
/// Clock Prescaler Register.
pub const CLKPR: *mut u8 = 0x5C as *mut u8;
/// Stack Pointer.
pub const SP: *mut u16 = 0x5D as *mut u16;
/// Stack Pointer  low byte.
pub const SPL: *mut u8 = 0x5D as *mut u8;
/// Stack Pointer  high byte.
pub const SPH: *mut u8 = 0x5E as *mut u8;
/// Status Register.
pub const SREG: *mut u8 = 0x5F as *mut u8;
/// Watchdog Timer Control Register.
pub const WDTCR: *mut u8 = 0x60 as *mut u8;
/// Sensor Interrupt Mask register.
pub const SIMSK: *mut u8 = 0x61 as *mut u8;
/// Temperature Sensor Control Register.
pub const TSCR: *mut u8 = 0x64 as *mut u8;
/// SRC-Oscillator Calibration Register.
pub const SRCCAL: *mut u8 = 0x65 as *mut u8;
/// FRC-Oscillator Calibration Register.
pub const FRCCAL: *mut u8 = 0x66 as *mut u8;
/// Motion Sensor Voltage Calibration Register.
pub const MSVCAL: *mut u8 = 0x67 as *mut u8;
/// External Interrupt Control Register.
pub const EICRA: *mut u8 = 0x69 as *mut u8;
/// Pin Change Mask Register 0.
pub const PCMSK0: *mut u8 = 0x6A as *mut u8;
/// Pin Change Mask Register 1.
pub const PCMSK1: *mut u8 = 0x6B as *mut u8;
/// Pin Change Mask Register 2.
pub const PCMSK2: *mut u8 = 0x6C as *mut u8;
/// Timer 2 Input Capture Register Low Byte.
pub const T2ICRL: *mut u8 = 0x6E as *mut u8;
/// Timer 2 Input Capture Register High Byte.
pub const T2ICR: *mut u8 = 0x6F as *mut u8;
/// Timer2 Compare Register  Bytes low byte.
pub const T2CORL: *mut u8 = 0x70 as *mut u8;
/// Timer2 Compare Register  Bytes.
pub const T2COR: *mut u16 = 0x70 as *mut u16;
/// Timer2 Compare Register  Bytes high byte.
pub const T2CORH: *mut u8 = 0x71 as *mut u8;
/// Timer 2 Mode Register A.
pub const T2MRA: *mut u8 = 0x72 as *mut u8;
/// Timer 2 Mode Register B.
pub const T2MRB: *mut u8 = 0x73 as *mut u8;
/// Timer 2 Interrupt Mask Register.
pub const T2IMR: *mut u8 = 0x74 as *mut u8;
/// Timer3 Input Capture Register  Bytes low byte.
pub const T3ICRL: *mut u8 = 0x76 as *mut u8;
/// Timer3 Input Capture Register  Bytes.
pub const T3ICR: *mut u16 = 0x76 as *mut u16;
/// Timer3 Input Capture Register  Bytes high byte.
pub const T3ICRH: *mut u8 = 0x77 as *mut u8;
/// Timer3 COmpare Register A  Bytes low byte.
pub const T3CORAL: *mut u8 = 0x78 as *mut u8;
/// Timer3 COmpare Register A  Bytes.
pub const T3CORA: *mut u16 = 0x78 as *mut u16;
/// Timer3 COmpare Register A  Bytes high byte.
pub const T3CORAH: *mut u8 = 0x79 as *mut u8;
/// Timer3 COmpare Register B  Bytes.
pub const T3CORB: *mut u16 = 0x7A as *mut u16;
/// Timer3 COmpare Register B  Bytes low byte.
pub const T3CORBL: *mut u8 = 0x7A as *mut u8;
/// Timer3 COmpare Register B  Bytes high byte.
pub const T3CORBH: *mut u8 = 0x7B as *mut u8;
/// Timer 3 Mode Register A.
pub const T3MRA: *mut u8 = 0x7C as *mut u8;
/// Timer 3 Mode Register B.
pub const T3MRB: *mut u8 = 0x7D as *mut u8;
/// Timer 3 Control Register B.
pub const T3CRB: *mut u8 = 0x7E as *mut u8;
/// Timer3 Interrupt Mask Register.
pub const T3IMR: *mut u8 = 0x7F as *mut u8;
/// Low Frequency Interrupt Mask Register.
pub const LFIMR: *mut u8 = 0x81 as *mut u8;
/// Low Frequency Receiver Control Register.
pub const LFRCR: *mut u8 = 0x82 as *mut u8;
/// LF Header Compare Register.
pub const LFHCR: *mut u8 = 0x83 as *mut u8;
/// LF ID Compare Register  low byte.
pub const LFIDCL: *mut u8 = 0x84 as *mut u8;
/// LF ID Compare Register.
pub const LFIDC: *mut u16 = 0x84 as *mut u16;
/// LF ID Compare Register  high byte.
pub const LFIDCH: *mut u8 = 0x85 as *mut u8;
/// LF Calibration Register  Bytes.
pub const LFCAL: *mut u16 = 0x86 as *mut u16;
/// LF Calibration Register  Bytes low byte.
pub const LFCALL: *mut u8 = 0x86 as *mut u8;
/// LF Calibration Register  Bytes high byte.
pub const LFCALH: *mut u8 = 0x87 as *mut u8;