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//! The AVR ATA5791 microcontroller
//!
//! # Variants
//! |        | Pinout | Package | Operating temperature | Operating voltage | Max speed |
//! |--------|--------|---------|-----------------------|-------------------|-----------|
//! | standard |  |  | 0°C - 0°C | 1.9V - 3.6V | 0 MHz |
//!
//! # Registers by module (not exhaustive)
//!
//! ## EEPROM modules
//!
//! * EEPROM

pub const LOW: *mut u8 = 0x0 as *mut u8;
pub const LOCKBIT: *mut u8 = 0x0 as *mut u8;
/// Port B Input Pins.
pub const PINB: *mut u8 = 0x23 as *mut u8;
/// Port B Data Direction Register.
pub const DDRB: *mut u8 = 0x24 as *mut u8;
/// Port B Data Register.
pub const PORTB: *mut u8 = 0x25 as *mut u8;
/// Port C Input Pins.
pub const PINC: *mut u8 = 0x26 as *mut u8;
/// Port C Data Direction Register.
pub const DDRC: *mut u8 = 0x27 as *mut u8;
/// Port C Data Register.
pub const PORTC: *mut u8 = 0x28 as *mut u8;
/// Port D Input Pins.
pub const PIND: *mut u8 = 0x29 as *mut u8;
/// Port D Data Direction Register.
pub const DDRD: *mut u8 = 0x2A as *mut u8;
/// Port D Data Register.
pub const PORTD: *mut u8 = 0x2B as *mut u8;
/// Timer3 Control Register 2.
pub const T3CR2: *mut u8 = 0x2C as *mut u8;
/// Transponder Control Register.
pub const TPCR: *mut u8 = 0x2D as *mut u8;
/// Transponder Status & Flag Register.
pub const TPFR: *mut u8 = 0x2E as *mut u8;
/// Clock Management Control Register.
pub const CMCR: *mut u8 = 0x2F as *mut u8;
/// Clock Management Status Register.
pub const CMSR: *mut u8 = 0x30 as *mut u8;
/// Timer 2 Control Register.
pub const T2CR: *mut u8 = 0x31 as *mut u8;
/// Timer 3 Control Register.
pub const T3CR: *mut u8 = 0x32 as *mut u8;
/// AES Control Register.
pub const AESCR: *mut u8 = 0x33 as *mut u8;
/// AES Status Register.
pub const AESSR: *mut u8 = 0x34 as *mut u8;
/// Timer Modulator Interrupt Flag Register.
pub const TMIFR: *mut u8 = 0x35 as *mut u8;
/// Voltage Monitor Status Register.
pub const VMSR: *mut u8 = 0x36 as *mut u8;
/// Pin Change Interrupt Flag Register.
pub const PCIFR: *mut u8 = 0x37 as *mut u8;
/// LF Flag Register.
pub const LFFR: *mut u8 = 0x38 as *mut u8;
/// Timer0 Interrupt Flag Register.
pub const T0IFR: *mut u8 = 0x39 as *mut u8;
/// Timer1 Interrupt Flag Register.
pub const T1IFR: *mut u8 = 0x3A as *mut u8;
/// Timer2 Interrupt Flag Register.
pub const T2IFR: *mut u8 = 0x3B as *mut u8;
/// Timer3 Interrupt Flag Register.
pub const T3IFR: *mut u8 = 0x3C as *mut u8;
/// External Interrupt Flag Register.
pub const EIFR: *mut u8 = 0x3D as *mut u8;
/// General Purpose I/O Register 0.
pub const GPIOR: *mut u8 = 0x3E as *mut u8;
/// EEPROM Control Register.
pub const EECR: *mut u8 = 0x3F as *mut u8;
/// EEPROM Data Register.
pub const EEDR: *mut u8 = 0x40 as *mut u8;
/// EEPROM Address Register  Bytes low byte.
pub const EEARL: *mut u8 = 0x41 as *mut u8;
/// EEPROM Address Register  Bytes.
pub const EEAR: *mut u16 = 0x41 as *mut u16;
/// EEPROM Address Register  Bytes high byte.
pub const EEARH: *mut u8 = 0x42 as *mut u8;
/// EEPROM Protect Register.
pub const EEPR: *mut u8 = 0x43 as *mut u8;
/// EEPROM Error Correction Code Register.
pub const EECCR: *mut u8 = 0x44 as *mut u8;
/// EEPROM Control Register 2.
pub const EECR2: *mut u8 = 0x45 as *mut u8;
/// Pin Change Interrupt Control Register.
pub const PCICR: *mut u8 = 0x46 as *mut u8;
/// External Interrupt Mask Register.
pub const EIMSK: *mut u8 = 0x47 as *mut u8;
/// Timer Modulator Data Register.
pub const TMDR: *mut u8 = 0x48 as *mut u8;
/// AES Data Register.
pub const AESDR: *mut u8 = 0x49 as *mut u8;
/// AES Key Register.
pub const AESKR: *mut u8 = 0x4A as *mut u8;
/// Voltage Monitor Control Register.
pub const VMCR: *mut u8 = 0x4B as *mut u8;
/// SPI Control Register.
pub const SPCR: *mut u8 = 0x4C as *mut u8;
/// SPI Status Register.
pub const SPSR: *mut u8 = 0x4D as *mut u8;
/// SPI Data Register.
pub const SPDR: *mut u8 = 0x4E as *mut u8;
/// Low Frequency Receiver Control Register 0.
pub const LFCR0: *mut u8 = 0x4F as *mut u8;
/// LF receiver Control Register 1.
pub const LFCR1: *mut u8 = 0x50 as *mut u8;
/// LF Receiver Data Buffer.
pub const LFRDB: *mut u8 = 0x52 as *mut u8;
/// Sleep Mode Control Register.
pub const SMCR: *mut u8 = 0x53 as *mut u8;
/// MCU Status Register.
pub const MCUSR: *mut u8 = 0x54 as *mut u8;
/// MCU Control Register.
pub const MCUCR: *mut u8 = 0x55 as *mut u8;
/// LF Status Register.
pub const LFSR: *mut u8 = 0x56 as *mut u8;
/// Store Program Memory Control Register.
pub const SPMCSR: *mut u8 = 0x57 as *mut u8;
/// Timer 1 Control Register.
pub const T1CR: *mut u8 = 0x58 as *mut u8;
/// Timer 0 Control Register.
pub const T0CR: *mut u8 = 0x59 as *mut u8;
/// Clock Management Interrupt Mask Register.
pub const CMIMR: *mut u8 = 0x5B as *mut u8;
/// Clock Prescaler Register.
pub const CLKPR: *mut u8 = 0x5C as *mut u8;
/// Stack Pointer  low byte.
pub const SPL: *mut u8 = 0x5D as *mut u8;
/// Stack Pointer.
pub const SP: *mut u16 = 0x5D as *mut u16;
/// Stack Pointer  high byte.
pub const SPH: *mut u8 = 0x5E as *mut u8;
/// Status Register.
pub const SREG: *mut u8 = 0x5F as *mut u8;
/// Watchdog Timer Control Register.
pub const WDTCR: *mut u8 = 0x60 as *mut u8;
/// Power Reduction Register.
pub const PRR0: *mut u8 = 0x63 as *mut u8;
/// Power Reduction Register.
pub const PRR1: *mut u8 = 0x64 as *mut u8;
/// SRC-Oscillator Calibration Register.
pub const SRCCAL: *mut u8 = 0x65 as *mut u8;
/// FRC-Oscillator Calibration Register.
pub const FRCCAL: *mut u8 = 0x66 as *mut u8;
/// External Interrupt Control Register.
pub const EICRA: *mut u8 = 0x69 as *mut u8;
/// Pin Change Mask Register 0.
pub const PCMSK0: *mut u8 = 0x6A as *mut u8;
/// Pin Change Mask Register 1.
pub const PCMSK1: *mut u8 = 0x6B as *mut u8;
/// LED Driver Control Register.
pub const LDCR: *mut u8 = 0x6D as *mut u8;
/// Timer 2 Counter Register.
pub const T2CNT: *mut u8 = 0x70 as *mut u8;
/// Timer2 Compare Register.
pub const T2COR: *mut u8 = 0x71 as *mut u8;
/// Timer 2 Mode Register.
pub const T2MR: *mut u8 = 0x73 as *mut u8;
/// Timer 2 Interrupt Mask Register.
pub const T2IMR: *mut u8 = 0x74 as *mut u8;
/// Timer3 COmpare2 Register.
pub const T3CO2R: *mut u8 = 0x75 as *mut u8;
/// Timer3 Counter Register.
pub const T3CNT: *mut u8 = 0x76 as *mut u8;
/// Timer3 COmpare Register.
pub const T3COR: *mut u8 = 0x77 as *mut u8;
/// Timer3 Input Capture Register.
pub const T3ICR: *mut u8 = 0x78 as *mut u8;
/// Timer 3 Mode Register A.
pub const T3MRA: *mut u8 = 0x79 as *mut u8;
/// Timer 3 Mode Register B.
pub const T3MRB: *mut u8 = 0x7A as *mut u8;
/// Timer3 Interrupt Mask Register.
pub const T3IMR: *mut u8 = 0x7B as *mut u8;
/// Timer Modulator Control Register.
pub const TMCR: *mut u8 = 0x7D as *mut u8;
/// Timer Modulator Mode Register.
pub const TMMR: *mut u8 = 0x7E as *mut u8;
/// Timer Modulator Interrupt Mask Register.
pub const TMIMR: *mut u8 = 0x7F as *mut u8;
/// LF Interrupt Mask Register.
pub const LFIMR: *mut u8 = 0x82 as *mut u8;
/// LF Clock Adjustment Data Register.
pub const LFCAD: *mut u8 = 0x83 as *mut u8;
/// LF ID 0 Data Register Byte 0.
pub const LFID00: *mut u8 = 0x84 as *mut u8;
/// LF ID 0 Data Register Byte 1.
pub const LFID01: *mut u8 = 0x85 as *mut u8;
/// LF ID 0 Data Register Byte 2.
pub const LFID02: *mut u8 = 0x86 as *mut u8;
/// LF ID 0 Data Register Byte 3.
pub const LFID03: *mut u8 = 0x87 as *mut u8;
/// LF ID 1 Data Register Byte 0.
pub const LFID10: *mut u8 = 0x88 as *mut u8;
/// LF ID 1 Data Register Byte 1.
pub const LFID11: *mut u8 = 0x89 as *mut u8;
/// LF ID 1 Data Register Byte 2.
pub const LFID12: *mut u8 = 0x8A as *mut u8;
/// LF ID 1 Data Register Byte 3.
pub const LFID13: *mut u8 = 0x8B as *mut u8;
/// LF Receive Data Register Byte 0.
pub const LFRD0: *mut u8 = 0x8C as *mut u8;
/// LF Receive Data Register Byte 1.
pub const LFRD1: *mut u8 = 0x8D as *mut u8;
/// LF Receive Data Register Byte 2.
pub const LFRD2: *mut u8 = 0x8E as *mut u8;
/// LF Receive Data Register Byte 3.
pub const LFRD3: *mut u8 = 0x8F as *mut u8;
/// LF Identifier 0 Mask Register.
pub const LFID0M: *mut u8 = 0x90 as *mut u8;
/// LF Identifier 1 Mask Register.
pub const LFID1M: *mut u8 = 0x91 as *mut u8;
/// LF Receive Data Frame Register.
pub const LFRDF: *mut u8 = 0x92 as *mut u8;
/// LF RSSI Data Register 1.
pub const LFRSD1: *mut u8 = 0x93 as *mut u8;
/// LF RSSI Data Register 2.
pub const LFRSD2: *mut u8 = 0x94 as *mut u8;
/// LF RSSI Data Register 3.
pub const LFRSD3: *mut u8 = 0x95 as *mut u8;
/// Low Frequency Channel Capacity select register 1.
pub const LFCC1: *mut u8 = 0x96 as *mut u8;
/// Low Frequency Channel Capacity select register 2.
pub const LFCC2: *mut u8 = 0x97 as *mut u8;
/// Low Frequency Channel Capacity select register 3.
pub const LFCC3: *mut u8 = 0x98 as *mut u8;
/// Low Frequency Receiver Quality Controll Register.
pub const LFQCR: *mut u8 = 0x99 as *mut u8;
/// Transponder Interrupt Mask Register.
pub const TPIMR: *mut u8 = 0x9C as *mut u8;
/// Real-Time Clock Control Register.
pub const RTCCR: *mut u8 = 0x9E as *mut u8;
/// Real Time Clock Data Register.
pub const RTCDR: *mut u8 = 0x9F as *mut u8;
/// Timer Modulator Manchester Data Register.
pub const TMMDR: *mut u8 = 0xA8 as *mut u8;
/// Timer Modulator Biphase Data Register.
pub const TMBDR: *mut u8 = 0xA9 as *mut u8;
/// Timer Modulator Transmit Data Register.
pub const TMTDR: *mut u8 = 0xAA as *mut u8;
/// Timer Modulator Shift Register.
pub const TMSR: *mut u8 = 0xAB as *mut u8;
/// CRC Polynomial Data Register.
pub const CRCPOL: *mut u8 = 0xAC as *mut u8;
/// CRC Data Register.
pub const CRCDR: *mut u8 = 0xAD as *mut u8;
/// CRC Control Register.
pub const CRCCR: *mut u8 = 0xAE as *mut u8;
/// CRC Status Register.
pub const CRCSR: *mut u8 = 0xAF as *mut u8;