//! The AVR ATA5783 microcontroller
//!
//! # Variants
//! |        | Pinout | Package | Operating temperature | Operating voltage | Max speed |
//! |--------|--------|---------|-----------------------|-------------------|-----------|
//! | standard |  |  | 0°C - 0°C | 2.4V - 5.5V | 0 MHz |
//!
//! # Registers by module (not exhaustive)
//!
//! ## EEPROM modules
//!
//! * EEPROM
//!
//! ## INT modules
//!
//! * INT

pub const LOCKBIT: *mut u8 = 0x0 as *mut u8;
pub const LOW: *mut u8 = 0x0 as *mut u8;
/// Power Reduction Register 0.
pub const PRR0: *mut u8 = 0x21 as *mut u8;
/// Power Reduction Register 1.
pub const PRR1: *mut u8 = 0x22 as *mut u8;
/// Power Reduction Register 2.
pub const PRR2: *mut u8 = 0x23 as *mut u8;
/// Rx DSP power reduction register.
pub const RDPR: *mut u8 = 0x24 as *mut u8;
/// Port B Input Pins.
pub const PINB: *mut u8 = 0x25 as *mut u8;
/// Port B Data Direction Register.
pub const DDRB: *mut u8 = 0x26 as *mut u8;
/// Port B Data Register.
pub const PORTB: *mut u8 = 0x27 as *mut u8;
/// Port C Input Pins.
pub const PINC: *mut u8 = 0x28 as *mut u8;
/// Port C Data Direction Register.
pub const DDRC: *mut u8 = 0x29 as *mut u8;
/// Port C Data Register.
pub const PORTC: *mut u8 = 0x2A as *mut u8;
/// Rx DSP status interrupt flag register.
pub const RDSIFR: *mut u8 = 0x2D as *mut u8;
/// MCU Control Register.
pub const MCUCR: *mut u8 = 0x2E as *mut u8;
/// Pin change Interrupt flag Register.
pub const PCIFR: *mut u8 = 0x2F as *mut u8;
/// Timer0 Control Register.
pub const T0CR: *mut u8 = 0x30 as *mut u8;
/// Timer1 control Register.
pub const T1CR: *mut u8 = 0x31 as *mut u8;
/// Timer2 Control Register.
pub const T2CR: *mut u8 = 0x32 as *mut u8;
/// Timer3 control Register.
pub const T3CR: *mut u8 = 0x33 as *mut u8;
/// Timer4 control Register.
pub const T4CR: *mut u8 = 0x34 as *mut u8;
/// Timer1 Interrupt Flag Register.
pub const T1IFR: *mut u8 = 0x35 as *mut u8;
/// Timer2 Interrupt Flag Register.
pub const T2IFR: *mut u8 = 0x36 as *mut u8;
/// Timer3 interrupt flag Register.
pub const T3IFR: *mut u8 = 0x37 as *mut u8;
/// Timer4 interrupt flag Register.
pub const T4IFR: *mut u8 = 0x38 as *mut u8;
/// Timer5 Interrupt Flag Register.
pub const T5IFR: *mut u8 = 0x39 as *mut u8;
/// General Purpose I/O Register 0.
pub const GPIOR0: *mut u8 = 0x3A as *mut u8;
/// General Purpose I/O Register 3.
pub const GPIOR3: *mut u8 = 0x3B as *mut u8;
/// General Purpose I/O Register 4.
pub const GPIOR4: *mut u8 = 0x3C as *mut u8;
/// General Purpose I/O Register 5.
pub const GPIOR5: *mut u8 = 0x3D as *mut u8;
/// General Purpose I/O Register 6.
pub const GPIOR6: *mut u8 = 0x3E as *mut u8;
/// EEPROM Control Register.
pub const EECR: *mut u8 = 0x3F as *mut u8;
/// EEPROM Data Register.
pub const EEDR: *mut u8 = 0x40 as *mut u8;
/// EEPROM Address Register.
pub const EEAR: *mut u16 = 0x41 as *mut u16;
/// EEPROM Address Register low byte.
pub const EEARL: *mut u8 = 0x41 as *mut u8;
/// EEPROM Address Register high byte.
pub const EEARH: *mut u8 = 0x42 as *mut u8;
/// EEPROM Protection Register.
pub const EEPR: *mut u8 = 0x43 as *mut u8;
/// General Purpose I/O Register 1.
pub const GPIOR1: *mut u8 = 0x44 as *mut u8;
/// General Purpose I/O Register 2.
pub const GPIOR2: *mut u8 = 0x45 as *mut u8;
/// Pin change Interrupt control Register.
pub const PCICR: *mut u8 = 0x46 as *mut u8;
/// External Interrupt Mask Register.
pub const EIMSK: *mut u8 = 0x47 as *mut u8;
/// External Interrupt Flag Register.
pub const EIFR: *mut u8 = 0x48 as *mut u8;
/// CRC Data Input Register.
pub const CRCDIR: *mut u8 = 0x49 as *mut u8;
/// Voltage Monitor Control and Status Register.
pub const VMCSR: *mut u8 = 0x4A as *mut u8;
/// MCU Status Register.
pub const MCUSR: *mut u8 = 0x4B as *mut u8;
/// SPI Control Register.
pub const SPCR: *mut u8 = 0x4C as *mut u8;
/// SPI Status Register.
pub const SPSR: *mut u8 = 0x4D as *mut u8;
/// SPI Data Register.
pub const SPDR: *mut u8 = 0x4E as *mut u8;
/// Timer0 Interrupt Flag Register.
pub const T0IFR: *mut u8 = 0x4F as *mut u8;
/// debugWire communication Register.
pub const DWDR: *mut u8 = 0x51 as *mut u8;
/// Rx DSP control register.
pub const RDCR: *mut u8 = 0x53 as *mut u8;
/// End Of Telegram Status on path A.
pub const EOTSA: *mut u8 = 0x54 as *mut u8;
/// End Of Telegram Conditions for path A.
pub const EOTCA: *mut u8 = 0x55 as *mut u8;
/// End Of Telegram Status on path B.
pub const EOTSB: *mut u8 = 0x56 as *mut u8;
/// End Of Telegram Conditions for path B.
pub const EOTCB: *mut u8 = 0x57 as *mut u8;
/// Sleep mode control Register.
pub const SMCR: *mut u8 = 0x58 as *mut u8;
/// Clock Management Control Register.
pub const CMCR: *mut u8 = 0x59 as *mut u8;
/// Clock Interrupt Mask Register.
pub const CMIMR: *mut u8 = 0x5A as *mut u8;
/// Clock Prescaler Register.
pub const CLPR: *mut u8 = 0x5B as *mut u8;
/// Store Program Memory Control and Status Register.
pub const SPMCSR: *mut u8 = 0x5C as *mut u8;
/// Stack Pointer.
pub const SP: *mut u16 = 0x5D as *mut u16;
/// Stack Pointer  low byte.
pub const SPL: *mut u8 = 0x5D as *mut u8;
/// Stack Pointer  high byte.
pub const SPH: *mut u8 = 0x5E as *mut u8;
/// Status Register.
pub const SREG: *mut u8 = 0x5F as *mut u8;
/// Frequency Synthesizer Enable register.
pub const FSEN: *mut u8 = 0x60 as *mut u8;
/// Fractional Frequency 1 Setting, Low Byte.
pub const FFREQ1L: *mut u8 = 0x64 as *mut u8;
/// Fractional Frequency 1 Setting, Middle Byte.
pub const FFREQ1M: *mut u8 = 0x65 as *mut u8;
/// Fractional Frequency 1 Setting, High Byte.
pub const FFREQ1H: *mut u8 = 0x66 as *mut u8;
/// Fractional Frequency 2 Setting, Low Byte.
pub const FFREQ2L: *mut u8 = 0x67 as *mut u8;
/// Fractional Frequency 2 Setting, Middle Byte.
pub const FFREQ2M: *mut u8 = 0x68 as *mut u8;
/// Fractional Frequency 2 Setting, High Byte.
pub const FFREQ2H: *mut u8 = 0x69 as *mut u8;
/// External Interrupt control Register.
pub const EICRA: *mut u8 = 0x6B as *mut u8;
/// Pin change Mask Register 0.
pub const PCMSK0: *mut u8 = 0x6C as *mut u8;
/// Pin change Mask Register 1.
pub const PCMSK1: *mut u8 = 0x6D as *mut u8;
/// Watchdog Timer0 control Register.
pub const WDTCR: *mut u8 = 0x6E as *mut u8;
/// Timer1 Counter Register.
pub const T1CNT: *mut u8 = 0x6F as *mut u8;
/// Timer1 Compare Register.
pub const T1COR: *mut u8 = 0x70 as *mut u8;
/// Timer1 Mode Register.
pub const T1MR: *mut u8 = 0x71 as *mut u8;
/// Timer1 Interrupt Mask Register.
pub const T1IMR: *mut u8 = 0x72 as *mut u8;
/// Timer2 Counter Register.
pub const T2CNT: *mut u8 = 0x73 as *mut u8;
/// Timer2 Compare Register.
pub const T2COR: *mut u8 = 0x74 as *mut u8;
/// Timer2 Mode Register.
pub const T2MR: *mut u8 = 0x75 as *mut u8;
/// Timer2 Interrupt Mask Register.
pub const T2IMR: *mut u8 = 0x76 as *mut u8;
/// Timer3 counter Register.
pub const T3CNT: *mut u16 = 0x77 as *mut u16;
/// Timer3 counter Register low byte.
pub const T3CNTL: *mut u8 = 0x77 as *mut u8;
/// Timer3 counter Register high byte.
pub const T3CNTH: *mut u8 = 0x78 as *mut u8;
/// Timer3 compare Register.
pub const T3COR: *mut u16 = 0x79 as *mut u16;
/// Timer3 compare Register low byte.
pub const T3CORL: *mut u8 = 0x79 as *mut u8;
/// Timer3 compare Register high byte.
pub const T3CORH: *mut u8 = 0x7A as *mut u8;
/// Timer3 input capture Register low byte.
pub const T3ICRL: *mut u8 = 0x7B as *mut u8;
/// Timer3 input capture Register.
pub const T3ICR: *mut u16 = 0x7B as *mut u16;
/// Timer3 input capture Register high byte.
pub const T3ICRH: *mut u8 = 0x7C as *mut u8;
/// Timer3 mode Register.
pub const T3MRA: *mut u8 = 0x7D as *mut u8;
/// Timer3 mode Register.
pub const T3MRB: *mut u8 = 0x7E as *mut u8;
/// Timer3 interrupt mask Register.
pub const T3IMR: *mut u8 = 0x7F as *mut u8;
/// Timer4 counter Register low byte.
pub const T4CNTL: *mut u8 = 0x80 as *mut u8;
/// Timer4 counter Register.
pub const T4CNT: *mut u16 = 0x80 as *mut u16;
/// Timer4 counter Register high byte.
pub const T4CNTH: *mut u8 = 0x81 as *mut u8;
/// Timer4 compare Register low byte.
pub const T4CORL: *mut u8 = 0x82 as *mut u8;
/// Timer4 compare Register.
pub const T4COR: *mut u16 = 0x82 as *mut u16;
/// Timer4 compare Register high byte.
pub const T4CORH: *mut u8 = 0x83 as *mut u8;
/// Timer4 input capture Register low byte.
pub const T4ICRL: *mut u8 = 0x84 as *mut u8;
/// Timer4 input capture Register.
pub const T4ICR: *mut u16 = 0x84 as *mut u16;
/// Timer4 input capture Register high byte.
pub const T4ICRH: *mut u8 = 0x85 as *mut u8;
/// Timer4 mode Register.
pub const T4MRA: *mut u8 = 0x86 as *mut u8;
/// Timer4 mode Register.
pub const T4MRB: *mut u8 = 0x87 as *mut u8;
/// Timer4 interrupt mask Register.
pub const T4IMR: *mut u8 = 0x88 as *mut u8;
/// Timer5 Output Compare Register.
pub const T5OCR: *mut u16 = 0x8A as *mut u16;
/// Timer5 Output Compare Register low byte.
pub const T5OCRL: *mut u8 = 0x8A as *mut u8;
/// Timer5 Output Compare Register high byte.
pub const T5OCRH: *mut u8 = 0x8B as *mut u8;
/// Timer5 Control Register.
pub const T5CCR: *mut u8 = 0x8C as *mut u8;
/// Timer5 Counter.
pub const T5CNT: *mut u16 = 0x8D as *mut u16;
/// Timer5 Counter low byte.
pub const T5CNTL: *mut u8 = 0x8D as *mut u8;
/// Timer5 Counter high byte.
pub const T5CNTH: *mut u8 = 0x8E as *mut u8;
/// Timer5 Interrupt Mask Register.
pub const T5IMR: *mut u8 = 0x8F as *mut u8;
/// General Timer/Counter Control Register.
pub const GTCCR: *mut u8 = 0x90 as *mut u8;
/// Start Of Telegram Status for path B.
pub const SOTSB: *mut u8 = 0x91 as *mut u8;
/// Start Of Telegram Status for path A.
pub const SOTSA: *mut u8 = 0x92 as *mut u8;
/// Start Of Telegram Conditions for path B.
pub const SOTCB: *mut u8 = 0x93 as *mut u8;
/// Start Of Telegram Conditions for path A.
pub const SOTCA: *mut u8 = 0x94 as *mut u8;
/// Telegram Status Register on Path B.
pub const TESRB: *mut u8 = 0x95 as *mut u8;
/// Telegram Status Register on Path A.
pub const TESRA: *mut u8 = 0x96 as *mut u8;
/// Rx DSP status interrupt mask register.
pub const RDSIMR: *mut u8 = 0x98 as *mut u8;
/// Rx DSP output control.
pub const RDOCR: *mut u8 = 0x99 as *mut u8;
/// Temperature Low byte.
pub const TEMPL: *mut u8 = 0x9B as *mut u8;
/// Temperature High byte.
pub const TEMPH: *mut u8 = 0x9C as *mut u8;
/// Symbol check configuration for data path B.
pub const SYCB: *mut u8 = 0x9D as *mut u8;
/// Symbol check configuration for data path A.
pub const SYCA: *mut u8 = 0x9E as *mut u8;
/// Received Frequency Offset vs Intermediate Frequency on path B.
pub const RXFOB: *mut u8 = 0x9F as *mut u8;
/// Received Frequency Offset vs Intermediate Frequency on path A.
pub const RXFOA: *mut u8 = 0xA0 as *mut u8;
/// Demodulator Mode for Path B.
pub const DMMB: *mut u8 = 0xA1 as *mut u8;
/// Demodulator Mode for path A.
pub const DMMA: *mut u8 = 0xA2 as *mut u8;
/// Demodulator Carrier Detect for path B.
pub const DMCDB: *mut u8 = 0xA3 as *mut u8;
/// Demodulator Carrier Detect for path A.
pub const DMCDA: *mut u8 = 0xA4 as *mut u8;
/// Demodulator Control Register for path B.
pub const DMCRB: *mut u8 = 0xA5 as *mut u8;
/// Demodulator Control Register for path A.
pub const DMCRA: *mut u8 = 0xA6 as *mut u8;
/// Demodulator Data Rate on path B.
pub const DMDRB: *mut u8 = 0xA7 as *mut u8;
/// Demodulator Data Rate on path A.
pub const DMDRA: *mut u8 = 0xA8 as *mut u8;
/// Channel Filter Configuration Register.
pub const CHCR: *mut u8 = 0xA9 as *mut u8;
/// Channel Filter Down Sampling Register.
pub const CHDN: *mut u8 = 0xAA as *mut u8;
/// Start-Frame ID Control for data path B.
pub const SFIDCB: *mut u8 = 0xAB as *mut u8;
/// Start-Frame ID Length for data path B.
pub const SFIDLB: *mut u8 = 0xAC as *mut u8;
/// Wake-Up Pattern Threshold for data path B.
pub const WUPTB: *mut u8 = 0xAD as *mut u8;
/// Wake-Up Pattern Length for data path B.
pub const WUPLB: *mut u8 = 0xAE as *mut u8;
/// Start-Frame ID byte 1 for data path B.
pub const SFID1B: *mut u8 = 0xAF as *mut u8;
/// Start-Frame ID byte 2 for data path B.
pub const SFID2B: *mut u8 = 0xB0 as *mut u8;
/// Start-Frame ID byte 3 for data path B.
pub const SFID3B: *mut u8 = 0xB1 as *mut u8;
/// Start-Frame ID byte 4 for data path B.
pub const SFID4B: *mut u8 = 0xB2 as *mut u8;
/// Wake-Up Pattern byte 1 for data path B.
pub const WUP1B: *mut u8 = 0xB3 as *mut u8;
/// Wake-Up Pattern byte 2 for data path B.
pub const WUP2B: *mut u8 = 0xB4 as *mut u8;
/// Wake-Up Pattern byte 3 for data path B.
pub const WUP3B: *mut u8 = 0xB5 as *mut u8;
/// Wake-Up Pattern byte 4 for data path B.
pub const WUP4B: *mut u8 = 0xB6 as *mut u8;
/// Start-Frame ID Control for data path A.
pub const SFIDCA: *mut u8 = 0xB7 as *mut u8;
/// Start-Frame ID Length for data path A.
pub const SFIDLA: *mut u8 = 0xB8 as *mut u8;
/// Wake-Up Pattern Threshold for data path A.
pub const WUPTA: *mut u8 = 0xB9 as *mut u8;
/// Wake-Up Pattern Length for data path A.
pub const WUPLA: *mut u8 = 0xBA as *mut u8;
/// Start-Frame ID byte 1 for data path A.
pub const SFID1A: *mut u8 = 0xBB as *mut u8;
/// Start-Frame ID byte 2 for data path A.
pub const SFID2A: *mut u8 = 0xBC as *mut u8;
/// Start-Frame ID byte 3 for data path A.
pub const SFID3A: *mut u8 = 0xBD as *mut u8;
/// Start-Frame ID byte 4 for data path A.
pub const SFID4A: *mut u8 = 0xBE as *mut u8;
/// Wake-Up Pattern byte 1 for data path A.
pub const WUP1A: *mut u8 = 0xBF as *mut u8;
/// Wake-Up Pattern byte 2 for data path A.
pub const WUP2A: *mut u8 = 0xC0 as *mut u8;
/// Wake-Up Pattern byte 3 for data path A.
pub const WUP3A: *mut u8 = 0xC1 as *mut u8;
/// Wake-Up Pattern byte 4 for data path A.
pub const WUP4A: *mut u8 = 0xC2 as *mut u8;
/// Clock output divider settings Register.
pub const CLKOD: *mut u8 = 0xC3 as *mut u8;
/// Clock output control Register.
pub const CLKOCR: *mut u8 = 0xC4 as *mut u8;
pub const XFUSE: *mut u8 = 0xC5 as *mut u8;
/// Slow RC oscillator calibration Register.
pub const SRCCAL: *mut u8 = 0xC6 as *mut u8;
/// Fast RC oscillator calibration Register.
pub const FRCCAL: *mut u8 = 0xC7 as *mut u8;
/// Clock management status Register.
pub const CMSR: *mut u8 = 0xC8 as *mut u8;
/// Clock management override control register.
pub const CMOCR: *mut u8 = 0xC9 as *mut u8;
/// Supply Interrupt Flag Register.
pub const SUPFR: *mut u8 = 0xCA as *mut u8;
/// Supply Control Register.
pub const SUPCR: *mut u8 = 0xCB as *mut u8;
/// Supply calibration register 2.
pub const SUPCA2: *mut u8 = 0xCD as *mut u8;
/// Supply calibration register 3.
pub const SUPCA3: *mut u8 = 0xCE as *mut u8;
/// Supply calibration register 4.
pub const SUPCA4: *mut u8 = 0xCF as *mut u8;
/// Calibration ready signature.
pub const CALRDY: *mut u8 = 0xD0 as *mut u8;
/// Voltage Monitor Calibration register.
pub const VMCAL: *mut u8 = 0xD1 as *mut u8;
/// Data FIFO Status Register.
pub const DFS: *mut u8 = 0xD2 as *mut u8;
/// Data FIFO Telegram Length low byte.
pub const DFTLL: *mut u8 = 0xD3 as *mut u8;
/// Data FIFO Telegram Length.
pub const DFTL: *mut u16 = 0xD3 as *mut u16;
/// Data FIFO Telegram Length high byte.
pub const DFTLH: *mut u8 = 0xD4 as *mut u8;
/// Data FIFO Fill Level Register.
pub const DFL: *mut u8 = 0xD5 as *mut u8;
/// Data FIFO Write Pointer.
pub const DFWP: *mut u8 = 0xD6 as *mut u8;
/// Data FIFO Read Pointer.
pub const DFRP: *mut u8 = 0xD7 as *mut u8;
/// Data FIFO Data Register.
pub const DFD: *mut u8 = 0xD8 as *mut u8;
/// Data FIFO Interrupt Mask Register.
pub const DFI: *mut u8 = 0xD9 as *mut u8;
/// Data FIFO Configuration Register.
pub const DFC: *mut u8 = 0xDA as *mut u8;
/// Support FIFO Status Register.
pub const SFS: *mut u8 = 0xDB as *mut u8;
/// Support FIFO Fill Level Register.
pub const SFL: *mut u8 = 0xDC as *mut u8;
/// Support FIFO Write Pointer.
pub const SFWP: *mut u8 = 0xDD as *mut u8;
/// Support FIFO Read Pointer.
pub const SFRP: *mut u8 = 0xDE as *mut u8;
/// Support FIFO Data Register.
pub const SFD: *mut u8 = 0xDF as *mut u8;
/// Support FIFO Interrupt Mask Register.
pub const SFI: *mut u8 = 0xE0 as *mut u8;
/// Support FIFO Configuration Register.
pub const SFC: *mut u8 = 0xE1 as *mut u8;
/// SSM Control Register.
pub const SSMCR: *mut u8 = 0xE2 as *mut u8;
/// SSM Rx Control Register.
pub const SSMRCR: *mut u8 = 0xE3 as *mut u8;
/// SSM Filter Bandwidth Register.
pub const SSMFBR: *mut u8 = 0xE4 as *mut u8;
/// SSM Run Register.
pub const SSMRR: *mut u8 = 0xE5 as *mut u8;
/// SSM Status Register.
pub const SSMSR: *mut u8 = 0xE6 as *mut u8;
/// SSM Interrupt Flag Register.
pub const SSMIFR: *mut u8 = 0xE7 as *mut u8;
/// SSM interrupt mask register.
pub const SSMIMR: *mut u8 = 0xE8 as *mut u8;
/// Master State Machine state register.
pub const MSMSTR: *mut u8 = 0xE9 as *mut u8;
/// SSM State Register.
pub const SSMSTR: *mut u8 = 0xEA as *mut u8;
/// SSM extended State Register.
pub const SSMXSR: *mut u8 = 0xEB as *mut u8;
/// Master State Machine Control Register 1.
pub const MSMCR1: *mut u8 = 0xEC as *mut u8;
/// Master State Machine Control Register 2.
pub const MSMCR2: *mut u8 = 0xED as *mut u8;
/// Master State Machine Control Register 3.
pub const MSMCR3: *mut u8 = 0xEE as *mut u8;
/// Master State Machine Control Register 4.
pub const MSMCR4: *mut u8 = 0xEF as *mut u8;
/// Get Telegram Control Register.
pub const GTCR: *mut u8 = 0xF0 as *mut u8;
/// Start Of Telegram Conditions 1 for Path A.
pub const SOTC1A: *mut u8 = 0xF1 as *mut u8;
/// Start Of Telegram Conditions 2 for Path A.
pub const SOTC2A: *mut u8 = 0xF2 as *mut u8;
/// Start Of Telegram Conditions 1 for Path B.
pub const SOTC1B: *mut u8 = 0xF3 as *mut u8;
/// Start Of Telegram Conditions 2 for Path B.
pub const SOTC2B: *mut u8 = 0xF4 as *mut u8;
/// End Of Telegram Conditions 1 for Path A.
pub const EOTC1A: *mut u8 = 0xF5 as *mut u8;
/// End Of Telegram Conditions 2 for Path A.
pub const EOTC2A: *mut u8 = 0xF6 as *mut u8;
/// End Of Telegram Conditions 3 for Path A.
pub const EOTC3A: *mut u8 = 0xF7 as *mut u8;
/// End Of Telegram Conditions 1 for Path B.
pub const EOTC1B: *mut u8 = 0xF8 as *mut u8;
/// End Of Telegram Conditions 2 for Path B.
pub const EOTC2B: *mut u8 = 0xF9 as *mut u8;
/// End Of Telegram Conditions 3 for Path B.
pub const EOTC3B: *mut u8 = 0xFA as *mut u8;
/// Wait check ok time out for path A.
pub const WCOTOA: *mut u8 = 0xFB as *mut u8;
/// Wait check ok time out for path B.
pub const WCOTOB: *mut u8 = 0xFC as *mut u8;
/// Start Of Telegram Time Out for path A.
pub const SOTTOA: *mut u8 = 0xFD as *mut u8;
/// Start Of Telegram Time Out for path B.
pub const SOTTOB: *mut u8 = 0xFE as *mut u8;
/// SSM Flow Control Register.
pub const SSMFCR: *mut u8 = 0xFF as *mut u8;
/// Front-End Status Register.
pub const FESR: *mut u8 = 0x100 as *mut u8;
/// Front-End Enable Register 1.
pub const FEEN1: *mut u8 = 0x101 as *mut u8;
/// Front-End Enable Register 2.
pub const FEEN2: *mut u8 = 0x102 as *mut u8;
/// Front-End LNA Bias Register.
pub const FELNA: *mut u8 = 0x103 as *mut u8;
/// Front-End VCO Tuning Register.
pub const FEVCT: *mut u8 = 0x106 as *mut u8;
/// Front-End RC Tuning Register.
pub const FEBT: *mut u8 = 0x107 as *mut u8;
/// Front-End Main and Swallow Control Register.
pub const FEMS: *mut u8 = 0x108 as *mut u8;
/// Front-End RC Tuning 4bit Register.
pub const FETN4: *mut u8 = 0x109 as *mut u8;
/// Front-End Control Register.
pub const FECR: *mut u8 = 0x10A as *mut u8;
/// Front-End VCO and PLL control.
pub const FEVCO: *mut u8 = 0x10B as *mut u8;
/// Front-End Antenna Level Detector Range.
pub const FEALR: *mut u8 = 0x10C as *mut u8;
/// Front-End ANTenna.
pub const FEANT: *mut u8 = 0x10D as *mut u8;
/// Front-End IF Amplifier BIAS.
pub const FEBIA: *mut u8 = 0x10E as *mut u8;
/// Rx Buffer configuration register 1.
pub const RXBC1: *mut u8 = 0x12F as *mut u8;
/// Rx Buffer configuration register 2.
pub const RXBC2: *mut u8 = 0x130 as *mut u8;
/// Rx data telegram length register low byte for data path B.
pub const RXTLLB: *mut u8 = 0x131 as *mut u8;
/// Rx data telegram length register high byte for data path B.
pub const RXTLHB: *mut u8 = 0x132 as *mut u8;
/// Rx CRC result register low byte for data path B.
pub const RXCRLB: *mut u8 = 0x133 as *mut u8;
/// Rx CRC result register high byte for data path B.
pub const RXCRHB: *mut u8 = 0x134 as *mut u8;
/// Rx CRC skip bit number for data path B.
pub const RXCSBB: *mut u8 = 0x135 as *mut u8;
/// Rx CRC Init value (16-bit RXCI) low byte for data path B.
pub const RXCILB: *mut u8 = 0x136 as *mut u8;
/// Rx CRC Init value (16-bit RXCI) high byte for data path B.
pub const RXCIHB: *mut u8 = 0x137 as *mut u8;
/// Rx CRC polynomial low byte for data path B.
pub const RXCPLB: *mut u8 = 0x138 as *mut u8;
/// Rx CRC polynomial (15 bit RXCPB) high byte for data path B.
pub const RXCPHB: *mut u8 = 0x139 as *mut u8;
/// Rx data shift register for data path B.
pub const RXDSB: *mut u8 = 0x13A as *mut u8;
/// Rx data telegram length register low byte for data path A.
pub const RXTLLA: *mut u8 = 0x13B as *mut u8;
/// Rx data telegram length register high byte for data path A.
pub const RXTLHA: *mut u8 = 0x13C as *mut u8;
/// Rx CRC result register low byte for data path A.
pub const RXCRLA: *mut u8 = 0x13D as *mut u8;
/// Rx CRC result register high byte for data path A.
pub const RXCRHA: *mut u8 = 0x13E as *mut u8;
/// Rx CRC skip bit number for data path A.
pub const RXCSBA: *mut u8 = 0x13F as *mut u8;
/// Rx CRC Init value (16-bit RXCI) low byte for data path A.
pub const RXCILA: *mut u8 = 0x140 as *mut u8;
/// Rx CRC Init value (16-bit RXCI) high byte for data path A.
pub const RXCIHA: *mut u8 = 0x141 as *mut u8;
/// Rx CRC polynomial low byte for data path A.
pub const RXCPLA: *mut u8 = 0x142 as *mut u8;
/// Rx CRC polynomial (15 bit RXCPA) high byte for data path A.
pub const RXCPHA: *mut u8 = 0x143 as *mut u8;
/// Rx data shift register for data path A.
pub const RXDSA: *mut u8 = 0x144 as *mut u8;
/// CRC Control Register.
pub const CRCCR: *mut u8 = 0x145 as *mut u8;
/// CRC Data Output Register.
pub const CRCDOR: *mut u8 = 0x146 as *mut u8;
/// ID Byte 0.
pub const IDB0: *mut u8 = 0x147 as *mut u8;
/// ID Byte 1.
pub const IDB1: *mut u8 = 0x148 as *mut u8;
/// ID Byte 2.
pub const IDB2: *mut u8 = 0x149 as *mut u8;
/// ID Byte 3.
pub const IDB3: *mut u8 = 0x14A as *mut u8;
/// ID Configuration.
pub const IDC: *mut u8 = 0x14B as *mut u8;
/// ID Status.
pub const IDS: *mut u8 = 0x14C as *mut u8;
/// RSSI Average Value.
pub const RSSAV: *mut u8 = 0x14D as *mut u8;
/// RSSI Peak Value.
pub const RSSPK: *mut u8 = 0x14E as *mut u8;
/// RSSI Low Threshold for Signal Check.
pub const RSSL: *mut u8 = 0x14F as *mut u8;
/// RSSI High Threshold for Signal Check.
pub const RSSH: *mut u8 = 0x150 as *mut u8;
/// RSSI Configuration Register.
pub const RSSC: *mut u8 = 0x151 as *mut u8;
/// DeBounce Control Register.
pub const DBCR: *mut u8 = 0x152 as *mut u8;
/// Debounce Timer Compare Register.
pub const DBTC: *mut u8 = 0x153 as *mut u8;
/// DeBounce Enable Port B.
pub const DBENB: *mut u8 = 0x154 as *mut u8;
/// DeBounce Enable Port C.
pub const DBENC: *mut u8 = 0x155 as *mut u8;
/// Debugging Support Switch.
pub const DBGSW: *mut u8 = 0x156 as *mut u8;
/// SPI FIFO Fill Status Register.
pub const SFFR: *mut u8 = 0x157 as *mut u8;
/// SPI FIFO Interrupt Register.
pub const SFIR: *mut u8 = 0x158 as *mut u8;
/// EEPROM Control Register 2.
pub const EECR2: *mut u8 = 0x159 as *mut u8;
/// Program Memory Status Register.
pub const PGMST: *mut u8 = 0x15A as *mut u8;
/// EEPROM Status Register.
pub const EEST: *mut u8 = 0x15B as *mut u8;
/// RSSI High IF Amplifier Gain.
pub const RSIFG: *mut u8 = 0x15C as *mut u8;
/// RSSI Low Band Damping Value.
pub const RSLDV: *mut u8 = 0x15D as *mut u8;
/// RSSI High Band Damping Value.
pub const RSHDV: *mut u8 = 0x15E as *mut u8;
/// RSSI Compensation Register.
pub const RSCOM: *mut u8 = 0x15F as *mut u8;