1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
//! The AVR ATtiny87 microcontroller
//!
//! # Variants
//! |        | Pinout | Package | Operating temperature | Operating voltage | Max speed |
//! |--------|--------|---------|-----------------------|-------------------|-----------|
//! | standard |  |  | 0°C - 0°C | 1.8V - 5.5V | 0 MHz |
//!
//! # Registers by module (not exhaustive)
//!
//! ## PORT modules
//!
//! * PORTA
//! * PORTB
//!
//! ## EEPROM modules
//!
//! * EEPROM
//!
//! ## ADC modules
//!
//! * ADC

pub const LOW: *mut u8 = 0x0 as *mut u8;
pub const LOCKBIT: *mut u8 = 0x0 as *mut u8;
pub const HIGH: *mut u8 = 0x1 as *mut u8;
pub const EXTENDED: *mut u8 = 0x2 as *mut u8;
/// Port A Input Pins.
pub const PINA: *mut u8 = 0x20 as *mut u8;
/// Port A Data Direction Register.
pub const DDRA: *mut u8 = 0x21 as *mut u8;
/// Port A Data Register.
pub const PORTA: *mut u8 = 0x22 as *mut u8;
/// Port B Input Pins.
pub const PINB: *mut u8 = 0x23 as *mut u8;
/// Port B Data Direction Register.
pub const DDRB: *mut u8 = 0x24 as *mut u8;
/// Port B Data Register.
pub const PORTB: *mut u8 = 0x25 as *mut u8;
/// Port Control Register.
pub const PORTCR: *mut u8 = 0x32 as *mut u8;
/// Timer/Counter0 Interrupt Flag Register.
pub const TIFR0: *mut u8 = 0x35 as *mut u8;
/// Timer/Counter1 Interrupt Flag register.
pub const TIFR1: *mut u8 = 0x36 as *mut u8;
/// Pin Change Interrupt Flag Register.
pub const PCIFR: *mut u8 = 0x3B as *mut u8;
/// External Interrupt Flag Register.
pub const EIFR: *mut u8 = 0x3C as *mut u8;
/// External Interrupt Mask Register.
pub const EIMSK: *mut u8 = 0x3D as *mut u8;
/// General purpose register 0.
pub const GPIOR0: *mut u8 = 0x3E as *mut u8;
/// EEPROM Control Register.
pub const EECR: *mut u8 = 0x3F as *mut u8;
/// EEPROM Data Register.
pub const EEDR: *mut u8 = 0x40 as *mut u8;
/// EEPROM Address Register  Bytes.
pub const EEAR: *mut u16 = 0x41 as *mut u16;
/// EEPROM Address Register  Bytes low byte.
pub const EEARL: *mut u8 = 0x41 as *mut u8;
/// EEPROM Address Register  Bytes high byte.
pub const EEARH: *mut u8 = 0x42 as *mut u8;
/// General Timer Counter Control register.
pub const GTCCR: *mut u8 = 0x43 as *mut u8;
/// Timer/Counter0 Control Register A.
pub const TCCR0A: *mut u8 = 0x45 as *mut u8;
/// Timer/Counter0 Control Register B.
pub const TCCR0B: *mut u8 = 0x46 as *mut u8;
/// Timer/Counter0.
pub const TCNT0: *mut u8 = 0x47 as *mut u8;
/// Timer/Counter0 Output Compare Register A.
pub const OCR0A: *mut u8 = 0x48 as *mut u8;
/// General Purpose register 1.
pub const GPIOR1: *mut u8 = 0x4A as *mut u8;
/// General Purpose IO register 2.
pub const GPIOR2: *mut u8 = 0x4B as *mut u8;
/// SPI Control Register.
pub const SPCR: *mut u8 = 0x4C as *mut u8;
/// SPI Status Register.
pub const SPSR: *mut u8 = 0x4D as *mut u8;
/// SPI Data Register.
pub const SPDR: *mut u8 = 0x4E as *mut u8;
/// Analog Comparator Control And Status Register.
pub const ACSR: *mut u8 = 0x50 as *mut u8;
/// DebugWire data register.
pub const DWDR: *mut u8 = 0x51 as *mut u8;
/// Sleep Mode Control Register.
pub const SMCR: *mut u8 = 0x53 as *mut u8;
/// MCU Status register.
pub const MCUSR: *mut u8 = 0x54 as *mut u8;
/// MCU Control Register.
pub const MCUCR: *mut u8 = 0x55 as *mut u8;
/// Store Program Memory Control Register.
pub const SPMCSR: *mut u8 = 0x57 as *mut u8;
/// Stack Pointer  Bytes low byte.
pub const SPL: *mut u8 = 0x5D as *mut u8;
/// Stack Pointer  Bytes.
pub const SP: *mut u16 = 0x5D as *mut u16;
/// Stack Pointer  Bytes high byte.
pub const SPH: *mut u8 = 0x5E as *mut u8;
/// Status Register.
pub const SREG: *mut u8 = 0x5F as *mut u8;
/// Watchdog Timer Control Register.
pub const WDTCR: *mut u8 = 0x60 as *mut u8;
/// Clock Prescale Register.
pub const CLKPR: *mut u8 = 0x61 as *mut u8;
/// Clock Control & Status Register.
pub const CLKCSR: *mut u8 = 0x62 as *mut u8;
/// Clock Selection Register.
pub const CLKSELR: *mut u8 = 0x63 as *mut u8;
/// Power Reduction Register.
pub const PRR: *mut u8 = 0x64 as *mut u8;
/// Oscillator Calibration Register.
pub const OSCCAL: *mut u8 = 0x66 as *mut u8;
/// Pin Change Interrupt Control Register.
pub const PCICR: *mut u8 = 0x68 as *mut u8;
/// External Interrupt Control Register.
pub const EICRA: *mut u8 = 0x69 as *mut u8;
/// Pin Change Mask Register 0.
pub const PCMSK0: *mut u8 = 0x6B as *mut u8;
/// Pin Change Mask Register 1.
pub const PCMSK1: *mut u8 = 0x6C as *mut u8;
/// Timer/Counter0 Interrupt Mask register.
pub const TIMSK0: *mut u8 = 0x6E as *mut u8;
/// Timer/Counter1 Interrupt Mask Register.
pub const TIMSK1: *mut u8 = 0x6F as *mut u8;
/// Analog Miscellaneous Control Register (Shared with AD_CONVERTER IO_MODULE).
pub const AMISCR: *mut u8 = 0x77 as *mut u8;
/// ADC Data Register  Bytes low byte.
pub const ADCL: *mut u8 = 0x78 as *mut u8;
/// ADC Data Register  Bytes.
pub const ADC: *mut u16 = 0x78 as *mut u16;
/// ADC Data Register  Bytes high byte.
pub const ADCH: *mut u8 = 0x79 as *mut u8;
/// The ADC Control and Status register A.
pub const ADCSRA: *mut u8 = 0x7A as *mut u8;
/// Analog Comparator & ADC Control and Status Register B (Shared with AD_CONVERTER IO_MODULE).
pub const ADCSRB: *mut u8 = 0x7B as *mut u8;
/// The ADC multiplexer Selection Register.
pub const ADMUX: *mut u8 = 0x7C as *mut u8;
/// Digital Input Disable Register 0.
pub const DIDR0: *mut u8 = 0x7E as *mut u8;
/// Digital Input Disable Register 1.
pub const DIDR1: *mut u8 = 0x7F as *mut u8;
/// Timer/Counter1 Control Register A.
pub const TCCR1A: *mut u8 = 0x80 as *mut u8;
/// Timer/Counter1 Control Register B.
pub const TCCR1B: *mut u8 = 0x81 as *mut u8;
/// Timer/Counter1 Control Register C.
pub const TCCR1C: *mut u8 = 0x82 as *mut u8;
/// Timer/Counter1 Control Register D.
pub const TCCR1D: *mut u8 = 0x83 as *mut u8;
/// Timer/Counter1  Bytes low byte.
pub const TCNT1L: *mut u8 = 0x84 as *mut u8;
/// Timer/Counter1  Bytes.
pub const TCNT1: *mut u16 = 0x84 as *mut u16;
/// Timer/Counter1  Bytes high byte.
pub const TCNT1H: *mut u8 = 0x85 as *mut u8;
/// Timer/Counter1 Input Capture Register  Bytes low byte.
pub const ICR1L: *mut u8 = 0x86 as *mut u8;
/// Timer/Counter1 Input Capture Register  Bytes.
pub const ICR1: *mut u16 = 0x86 as *mut u16;
/// Timer/Counter1 Input Capture Register  Bytes high byte.
pub const ICR1H: *mut u8 = 0x87 as *mut u8;
/// Timer/Counter1 Output Compare Register A  Bytes.
pub const OCR1A: *mut u16 = 0x88 as *mut u16;
/// Timer/Counter1 Output Compare Register A  Bytes low byte.
pub const OCR1AL: *mut u8 = 0x88 as *mut u8;
/// Timer/Counter1 Output Compare Register A  Bytes high byte.
pub const OCR1AH: *mut u8 = 0x89 as *mut u8;
/// Timer/Counter1 Output Compare Register B  Bytes low byte.
pub const OCR1BL: *mut u8 = 0x8A as *mut u8;
/// Timer/Counter1 Output Compare Register B  Bytes.
pub const OCR1B: *mut u16 = 0x8A as *mut u16;
/// Timer/Counter1 Output Compare Register B  Bytes high byte.
pub const OCR1BH: *mut u8 = 0x8B as *mut u8;
/// Asynchronous Status Register.
pub const ASSR: *mut u8 = 0xB6 as *mut u8;
/// USI Control Register.
pub const USICR: *mut u8 = 0xB8 as *mut u8;
/// USI Status Register.
pub const USISR: *mut u8 = 0xB9 as *mut u8;
/// USI Data Register.
pub const USIDR: *mut u8 = 0xBA as *mut u8;
/// USI Buffer Register.
pub const USIBR: *mut u8 = 0xBB as *mut u8;
/// USI Pin Position.
pub const USIPP: *mut u8 = 0xBC as *mut u8;
/// LIN Control Register.
pub const LINCR: *mut u8 = 0xC8 as *mut u8;
/// LIN Status and Interrupt Register.
pub const LINSIR: *mut u8 = 0xC9 as *mut u8;
/// LIN Enable Interrupt Register.
pub const LINENIR: *mut u8 = 0xCA as *mut u8;
/// LIN Error Register.
pub const LINERR: *mut u8 = 0xCB as *mut u8;
/// LIN Bit Timing Register.
pub const LINBTR: *mut u8 = 0xCC as *mut u8;
/// LIN Baud Rate Low Register.
pub const LINBRRL: *mut u8 = 0xCD as *mut u8;
/// LIN Baud Rate High Register.
pub const LINBRRH: *mut u8 = 0xCE as *mut u8;
/// LIN Data Length Register.
pub const LINDLR: *mut u8 = 0xCF as *mut u8;
/// LIN Identifier Register.
pub const LINIDR: *mut u8 = 0xD0 as *mut u8;
/// LIN Data Buffer Selection Register.
pub const LINSEL: *mut u8 = 0xD1 as *mut u8;
/// LIN Data Register.
pub const LINDAT: *mut u8 = 0xD2 as *mut u8;