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//! The AVR ATtiny102 microcontroller
//!
//! # Variants
//! |        | Pinout | Package | Operating temperature | Operating voltage | Max speed |
//! |--------|--------|---------|-----------------------|-------------------|-----------|
//! | ATtiny102-M7R  | SOIC_8 | UDFN8 | -40°C - 105°C | 1.8V - 5.5V | 12 MHz |
//! | ATtiny102F-M7R | SOIC_8 | UDFN8 | -40°C - 105°C | 1.8V - 5.5V | 12 MHz |
//! | ATtiny102-SSNR  | SOIC_8 | SOIC8 | -40°C - 105°C | 1.8V - 5.5V | 12 MHz |
//! | ATtiny102F-SSNR | SOIC_8 | SOIC8 | -40°C - 105°C | 1.8V - 5.5V | 12 MHz |
//! | ATtiny102-M8R  | SOIC_8 | UDFN8 | -40°C - 125°C | 1.8V - 5.5V | 12 MHz |
//! | ATtiny102F-M8R | SOIC_8 | UDFN8 | -40°C - 125°C | 1.8V - 5.5V | 12 MHz |
//! | ATtiny102-SSFR  | SOIC_8 | SOIC8 | -40°C - 125°C | 1.8V - 5.5V | 12 MHz |
//! | ATtiny102F-SSFR | SOIC_8 | SOIC8 | -40°C - 125°C | 1.8V - 5.5V | 12 MHz |
//!
//! # Registers by module (not exhaustive)
//!
//! ## PORT modules
//!
//! * PORTA
//!     * PA0 (PA0)
//!     * PA1 (PA1)
//!     * PA2 (PA2)
//! * PORTB
//!     * PB1 (PB1)
//!     * PB2 (PB2)
//!     * PB3 (PB3)
//!
//! ## ADC modules
//!
//! * ADC
//!     * PA0 (PA0)
//!     * PA1 (PA1)
//!     * PB1 (PB1)
//!     * PB2 (PB2)
//!     * PB3 (PB3)
//!
//! ## USART modules
//!
//! * USART
//!     * PB1 (PB1)
//!     * PB2 (PB2)
//!     * PB3 (PB3)

pub const LOCKBIT: *mut u8 = 0x0 as *mut u8;
pub const BYTE0: *mut u8 = 0x0 as *mut u8;
/// Input Pins, Port A.
pub const PINA: *mut u8 = 0x0 as *mut u8;
/// Data Direction Register, Port A.
pub const DDRA: *mut u8 = 0x1 as *mut u8;
/// Port A Data register.
pub const PORTA: *mut u8 = 0x2 as *mut u8;
/// Pull-up Enable Control Register for PORTA.
pub const PUEA: *mut u8 = 0x3 as *mut u8;
/// Input Pins, Port B.
pub const PINB: *mut u8 = 0x4 as *mut u8;
/// Data Direction Register, Port B.
pub const DDRB: *mut u8 = 0x5 as *mut u8;
/// Port B Data register.
pub const PORTB: *mut u8 = 0x6 as *mut u8;
/// Pull-up Enable Control Register for PORTB.
pub const PUEB: *mut u8 = 0x7 as *mut u8;
/// USART I/O Data Register.
pub const UDR: *mut u8 = 0x8 as *mut u8;
/// USART Baud Rate Register  Bytes.
pub const UBRR: *mut u16 = 0x9 as *mut u16;
/// USART Baud Rate Register  Bytes low byte.
pub const UBRRL: *mut u8 = 0x9 as *mut u8;
/// USART Baud Rate Register  Bytes high byte.
pub const UBRRH: *mut u8 = 0xA as *mut u8;
/// USART Control and Status Register D.
pub const UCSRD: *mut u8 = 0xB as *mut u8;
/// USART Control and Status Register C.
pub const UCSRC: *mut u8 = 0xC as *mut u8;
/// USART Control and Status Register B.
pub const UCSRB: *mut u8 = 0xD as *mut u8;
/// USART Control and Status Register A.
pub const UCSRA: *mut u8 = 0xE as *mut u8;
/// Pin Change Mask Register 0.
pub const PCMSK0: *mut u8 = 0xF as *mut u8;
/// Pin Change Mask Register 1.
pub const PCMSK1: *mut u8 = 0x10 as *mut u8;
/// Pin Change Interrupt Flag Register.
pub const PCIFR: *mut u8 = 0x11 as *mut u8;
/// Pin Change Interrupt Control Register.
pub const PCICR: *mut u8 = 0x12 as *mut u8;
/// External Interrupt Mask register.
pub const EIMSK: *mut u8 = 0x13 as *mut u8;
/// External Interrupt Flag register.
pub const EIFR: *mut u8 = 0x14 as *mut u8;
/// External Interrupt Control Register A.
pub const EICRA: *mut u8 = 0x15 as *mut u8;
/// Port Control Register.
pub const PORTCR: *mut u8 = 0x16 as *mut u8;
pub const DIDR0: *mut u8 = 0x17 as *mut u8;
/// ADC Data Register Low.
pub const ADCL: *mut u8 = 0x19 as *mut u8;
/// ADC Data Register High.
pub const ADCH: *mut u8 = 0x1A as *mut u8;
/// The ADC multiplexer Selection Register.
pub const ADMUX: *mut u8 = 0x1B as *mut u8;
/// The ADC Control and Status register B.
pub const ADCSRB: *mut u8 = 0x1C as *mut u8;
/// The ADC Control and Status register A.
pub const ADCSRA: *mut u8 = 0x1D as *mut u8;
/// Analog Comparator Control And Status Register B.
pub const ACSRB: *mut u8 = 0x1E as *mut u8;
/// Analog Comparator Control And Status Register A.
pub const ACSRA: *mut u8 = 0x1F as *mut u8;
/// Input Capture Register  Bytes.
pub const ICR0: *mut u16 = 0x22 as *mut u16;
/// Input Capture Register  Bytes low byte.
pub const ICR0L: *mut u8 = 0x22 as *mut u8;
/// Input Capture Register  Bytes high byte.
pub const ICR0H: *mut u8 = 0x23 as *mut u8;
/// Timer/Counter0 Output Compare Register B.
pub const OCR0B: *mut u16 = 0x24 as *mut u16;
/// Timer/Counter0 Output Compare Register B  low byte.
pub const OCR0BL: *mut u8 = 0x24 as *mut u8;
/// Timer/Counter0 Output Compare Register B  high byte.
pub const OCR0BH: *mut u8 = 0x25 as *mut u8;
/// Timer/Counter 0 Output Compare Register A  low byte.
pub const OCR0AL: *mut u8 = 0x26 as *mut u8;
/// Timer/Counter 0 Output Compare Register A.
pub const OCR0A: *mut u16 = 0x26 as *mut u16;
/// Timer/Counter 0 Output Compare Register A  high byte.
pub const OCR0AH: *mut u8 = 0x27 as *mut u8;
/// Timer/Counter0  low byte.
pub const TCNT0L: *mut u8 = 0x28 as *mut u8;
/// Timer/Counter0.
pub const TCNT0: *mut u16 = 0x28 as *mut u16;
/// Timer/Counter0  high byte.
pub const TCNT0H: *mut u8 = 0x29 as *mut u8;
/// Overflow Interrupt Enable.
pub const TIFR0: *mut u8 = 0x2A as *mut u8;
/// Timer Interrupt Mask Register 0.
pub const TIMSK0: *mut u8 = 0x2B as *mut u8;
/// Timer/Counter 0 Control Register C.
pub const TCCR0C: *mut u8 = 0x2C as *mut u8;
/// Timer/Counter 0 Control Register B.
pub const TCCR0B: *mut u8 = 0x2D as *mut u8;
/// Timer/Counter 0 Control Register A.
pub const TCCR0A: *mut u8 = 0x2E as *mut u8;
/// General Timer/Counter Control Register.
pub const GTCCR: *mut u8 = 0x2F as *mut u8;
/// Watchdog Timer Control and Status Register.
pub const WDTCSR: *mut u8 = 0x31 as *mut u8;
/// Non-Volatile Memory Control and Status Register.
pub const NVMCSR: *mut u8 = 0x32 as *mut u8;
/// Non-Volatile Memory Command.
pub const NVMCMD: *mut u8 = 0x33 as *mut u8;
/// Vcc Level Monitoring Control and Status Register.
pub const VLMCSR: *mut u8 = 0x34 as *mut u8;
/// Power Reduction Register.
pub const PRR: *mut u8 = 0x35 as *mut u8;
/// Clock Prescale Register.
pub const CLKPSR: *mut u8 = 0x36 as *mut u8;
/// Clock Main Settings Register.
pub const CLKMSR: *mut u8 = 0x37 as *mut u8;
/// Oscillator Calibration Value.
pub const OSCCAL: *mut u8 = 0x39 as *mut u8;
/// Sleep Mode Control Register.
pub const SMCR: *mut u8 = 0x3A as *mut u8;
/// Reset Flag Register.
pub const RSTFLR: *mut u8 = 0x3B as *mut u8;
/// Configuration Change Protection.
pub const CCP: *mut u8 = 0x3C as *mut u8;
/// Stack Pointer  low byte.
pub const SPL: *mut u8 = 0x3D as *mut u8;
/// Stack Pointer.
pub const SP: *mut u16 = 0x3D as *mut u16;
/// Stack Pointer  high byte.
pub const SPH: *mut u8 = 0x3E as *mut u8;
/// Status Register.
pub const SREG: *mut u8 = 0x3F as *mut u8;