//! The AVR ATA5702M322 microcontroller
//!
//! # Variants
//! |        | Pinout | Package | Operating temperature | Operating voltage | Max speed |
//! |--------|--------|---------|-----------------------|-------------------|-----------|
//! | standard |  |  | 0°C - 0°C | 2.1V - 4.2V | 0 MHz |
//!
//! # Registers by module (not exhaustive)
//!
//! ## EEPROM modules
//!
//! * EEPROM
//!
//! ## INT modules
//!
//! * INT

pub const LOCKBIT: *mut u8 = 0x0 as *mut u8;
pub const LOW: *mut u8 = 0x0 as *mut u8;
/// General Purpose I/O Register 0.
pub const GPIOR0: *mut u8 = 0x20 as *mut u8;
/// Power reduction Register 1.
pub const PRR1: *mut u8 = 0x21 as *mut u8;
/// Power reduction register 2.
pub const PRR2: *mut u8 = 0x22 as *mut u8;
/// Port B Input Pins.
pub const PINB: *mut u8 = 0x23 as *mut u8;
/// Port B Data Direction Register.
pub const DDRB: *mut u8 = 0x24 as *mut u8;
/// Port B Data Register.
pub const PORTB: *mut u8 = 0x25 as *mut u8;
/// Port C Input Pins.
pub const PINC: *mut u8 = 0x26 as *mut u8;
/// Port C Data Direction Register.
pub const DDRC: *mut u8 = 0x27 as *mut u8;
/// Port C Data Register.
pub const PORTC: *mut u8 = 0x28 as *mut u8;
/// Port D Input Pins.
pub const PIND: *mut u8 = 0x29 as *mut u8;
/// Port D Data Direction Register.
pub const DDRD: *mut u8 = 0x2A as *mut u8;
/// Port D Data Register.
pub const PORTD: *mut u8 = 0x2B as *mut u8;
/// Transponder Control 2 Register.
pub const TPCR2: *mut u8 = 0x2C as *mut u8;
/// Transponder Flag Register.
pub const TPFR: *mut u8 = 0x2D as *mut u8;
/// MCU control Register.
pub const MCUCR: *mut u8 = 0x2E as *mut u8;
/// Frequency Synthesizer Control Register.
pub const FSCR: *mut u8 = 0x2F as *mut u8;
/// Timer1 control Register.
pub const T1CR: *mut u8 = 0x31 as *mut u8;
/// Timer2 Control Register.
pub const T2CR: *mut u8 = 0x32 as *mut u8;
/// Timer3 control Register.
pub const T3CR: *mut u8 = 0x33 as *mut u8;
/// Timer4 control Register.
pub const T4CR: *mut u8 = 0x34 as *mut u8;
/// LF Timer Control Mode Register.
pub const LTCMR: *mut u8 = 0x35 as *mut u8;
/// EEPROM Control Register 2.
pub const EECR2: *mut u8 = 0x36 as *mut u8;
/// PH Telegram Configuration Register.
pub const PHTCR: *mut u8 = 0x37 as *mut u8;
/// LF Data FIFO Fill Level Register.
pub const LDFFL: *mut u8 = 0x38 as *mut u8;
/// LF Data FIFO Data Register.
pub const LDFD: *mut u8 = 0x39 as *mut u8;
/// Power reduction Register 0.
pub const PRR0: *mut u8 = 0x3A as *mut u8;
/// Protocol Handler Flag Register.
pub const PHFR: *mut u8 = 0x3B as *mut u8;
/// LF Receiver Flag Register.
pub const LFFR: *mut u8 = 0x3C as *mut u8;
/// AES Control Register.
pub const AESCR: *mut u8 = 0x3D as *mut u8;
/// AES Status Register.
pub const AESSR: *mut u8 = 0x3E as *mut u8;
/// EEPROM Control Register.
pub const EECR: *mut u8 = 0x3F as *mut u8;
/// EEPROM Data Register.
pub const EEDR: *mut u8 = 0x40 as *mut u8;
/// EEPROM Address Register.
pub const EEAR: *mut u16 = 0x41 as *mut u16;
/// EEPROM Address Register low byte.
pub const EEARL: *mut u8 = 0x41 as *mut u8;
/// EEPROM Address Register high byte.
pub const EEARH: *mut u8 = 0x42 as *mut u8;
/// EEPROM Protection Register.
pub const EEPR: *mut u8 = 0x43 as *mut u8;
/// General Purpose I/O Register 1.
pub const GPIOR1: *mut u8 = 0x44 as *mut u8;
/// General Purpose I/O Register 2.
pub const GPIOR2: *mut u8 = 0x45 as *mut u8;
/// Pin change Interrupt control Register.
pub const PCICR: *mut u8 = 0x46 as *mut u8;
/// External Interrupt Mask Register.
pub const EIMSK: *mut u8 = 0x47 as *mut u8;
/// External Interrupt Flag Register.
pub const EIFR: *mut u8 = 0x48 as *mut u8;
/// LF Data FIFO Clock Switch Register.
pub const LDFCKSW: *mut u8 = 0x49 as *mut u8;
/// Voltage Monitor Status and Control Register.
pub const VMSCR: *mut u8 = 0x4A as *mut u8;
/// MCU Status Register.
pub const MCUSR: *mut u8 = 0x4B as *mut u8;
/// SPI control Register.
pub const SPCR: *mut u8 = 0x4C as *mut u8;
/// SPI Status Register.
pub const SPSR: *mut u8 = 0x4D as *mut u8;
/// SPI Data Register.
pub const SPDR: *mut u8 = 0x4E as *mut u8;
/// LF Receiver Control Register 0.
pub const LFCR0: *mut u8 = 0x4F as *mut u8;
/// LF Receiver Control Register 1.
pub const LFCR1: *mut u8 = 0x50 as *mut u8;
/// Debug Wire Data Register.
pub const DWDR: *mut u8 = 0x51 as *mut u8;
/// Timer0 Interrupt Flag Register.
pub const T0IFR: *mut u8 = 0x52 as *mut u8;
/// Store Program Memory Control and Status Register.
pub const SPMCSR: *mut u8 = 0x57 as *mut u8;
/// Sleep mode control Register.
pub const SMCR: *mut u8 = 0x58 as *mut u8;
/// Transponder Status Register.
pub const TPSR: *mut u8 = 0x59 as *mut u8;
/// LF Receiver Control Register 2.
pub const LFCR2: *mut u8 = 0x5A as *mut u8;
/// LF Receiver Control Register 3.
pub const LFCR3: *mut u8 = 0x5B as *mut u8;
/// Stack Pointer.
pub const SP: *mut u16 = 0x5D as *mut u16;
/// Stack Pointer low byte.
pub const SPL: *mut u8 = 0x5D as *mut u8;
/// Stack Pointer high byte.
pub const SPH: *mut u8 = 0x5E as *mut u8;
/// Status Register.
pub const SREG: *mut u8 = 0x5F as *mut u8;
/// Frequency Synthesizer Enable register.
pub const FSEN: *mut u8 = 0x60 as *mut u8;
/// Frequency Synthesizer Filter Control Register.
pub const FSFCR: *mut u8 = 0x61 as *mut u8;
/// Gauss Clock Divider low byte.
pub const GACDIVL: *mut u8 = 0x62 as *mut u8;
/// Gauss Clock Divider.
pub const GACDIV: *mut u16 = 0x62 as *mut u16;
/// Gauss Clock Divider high byte.
pub const GACDIVH: *mut u8 = 0x63 as *mut u8;
/// Fractional Frequency 1 Setting, Low Byte.
pub const FFREQ1L: *mut u8 = 0x64 as *mut u8;
/// Fractional Frequency 1 Setting, Middle Byte.
pub const FFREQ1M: *mut u8 = 0x65 as *mut u8;
/// Fractional Frequency 1 Setting, High Byte.
pub const FFREQ1H: *mut u8 = 0x66 as *mut u8;
/// Fractional Frequency 2 Setting, Low Byte.
pub const FFREQ2L: *mut u8 = 0x67 as *mut u8;
/// Fractional Frequency 2 Setting, Middle Byte.
pub const FFREQ2M: *mut u8 = 0x68 as *mut u8;
/// Fractional Frequency 2 Setting, High Byte.
pub const FFREQ2H: *mut u8 = 0x69 as *mut u8;
/// Base Band Test Enable 2.
pub const BBTE2: *mut u8 = 0x6A as *mut u8;
/// External Interrupt control Register.
pub const EICRA: *mut u8 = 0x6B as *mut u8;
/// Pin change Mask Register 0.
pub const PCMSK0: *mut u8 = 0x6C as *mut u8;
/// Pin change Mask Register 1.
pub const PCMSK1: *mut u8 = 0x6D as *mut u8;
/// Watchdog Timer0 control Register.
pub const WDTCR: *mut u8 = 0x6E as *mut u8;
/// Timer1 Counter Register.
pub const T1CNT: *mut u8 = 0x6F as *mut u8;
/// Timer1 Compare Register.
pub const T1COR: *mut u8 = 0x70 as *mut u8;
/// Timer1 Mode Register.
pub const T1MR: *mut u8 = 0x71 as *mut u8;
/// Timer1 Interrupt Mask Register.
pub const T1IMR: *mut u8 = 0x72 as *mut u8;
/// Timer2 Counter Register.
pub const T2CNT: *mut u8 = 0x73 as *mut u8;
/// Timer2 Compare Register.
pub const T2COR: *mut u8 = 0x74 as *mut u8;
/// Timer2 Mode Register.
pub const T2MR: *mut u8 = 0x75 as *mut u8;
/// Timer2 Interrupt Mask Register.
pub const T2IMR: *mut u8 = 0x76 as *mut u8;
/// Timer3 counter Register low byte.
pub const T3CNTL: *mut u8 = 0x77 as *mut u8;
/// Timer3 counter Register.
pub const T3CNT: *mut u16 = 0x77 as *mut u16;
/// Timer3 counter Register high byte.
pub const T3CNTH: *mut u8 = 0x78 as *mut u8;
/// Timer3 compare Register.
pub const T3COR: *mut u16 = 0x79 as *mut u16;
/// Timer3 compare Register low byte.
pub const T3CORL: *mut u8 = 0x79 as *mut u8;
/// Timer3 compare Register high byte.
pub const T3CORH: *mut u8 = 0x7A as *mut u8;
/// Timer3 input capture Register.
pub const T3ICR: *mut u16 = 0x7B as *mut u16;
/// Timer3 input capture Register low byte.
pub const T3ICRL: *mut u8 = 0x7B as *mut u8;
/// Timer3 input capture Register high byte.
pub const T3ICRH: *mut u8 = 0x7C as *mut u8;
/// Timer3 mode Register.
pub const T3MRA: *mut u8 = 0x7D as *mut u8;
/// Timer3 mode Register.
pub const T3MRB: *mut u8 = 0x7E as *mut u8;
/// Timer3 interrupt mask Register.
pub const T3IMR: *mut u8 = 0x7F as *mut u8;
/// Timer4 counter Register low byte.
pub const T4CNTL: *mut u8 = 0x80 as *mut u8;
/// Timer4 counter Register.
pub const T4CNT: *mut u16 = 0x80 as *mut u16;
/// Timer4 counter Register high byte.
pub const T4CNTH: *mut u8 = 0x81 as *mut u8;
/// Timer4 compare Register low byte.
pub const T4CORL: *mut u8 = 0x82 as *mut u8;
/// Timer4 compare Register.
pub const T4COR: *mut u16 = 0x82 as *mut u16;
/// Timer4 compare Register high byte.
pub const T4CORH: *mut u8 = 0x83 as *mut u8;
/// Timer4 input capture Register.
pub const T4ICR: *mut u16 = 0x84 as *mut u16;
/// Timer4 input capture Register low byte.
pub const T4ICRL: *mut u8 = 0x84 as *mut u8;
/// Timer4 input capture Register high byte.
pub const T4ICRH: *mut u8 = 0x85 as *mut u8;
/// Timer4 mode Register.
pub const T4MRA: *mut u8 = 0x86 as *mut u8;
/// Timer4 mode Register.
pub const T4MRB: *mut u8 = 0x87 as *mut u8;
/// Timer4 interrupt mask Register.
pub const T4IMR: *mut u8 = 0x88 as *mut u8;
/// Timer5 Temp Register.
pub const T5TEMP: *mut u8 = 0x89 as *mut u8;
/// Timer5 Output Compare Register low byte.
pub const T5OCRL: *mut u8 = 0x8A as *mut u8;
/// Timer5 Output Compare Register.
pub const T5OCR: *mut u16 = 0x8A as *mut u16;
/// Timer5 Output Compare Register high byte.
pub const T5OCRH: *mut u8 = 0x8B as *mut u8;
/// Timer5 Control Register.
pub const T5CCR: *mut u8 = 0x8C as *mut u8;
/// Timer5 Counter low byte.
pub const T5CNTL: *mut u8 = 0x8D as *mut u8;
/// Timer5 Counter.
pub const T5CNT: *mut u16 = 0x8D as *mut u16;
/// Timer5 Counter high byte.
pub const T5CNTH: *mut u8 = 0x8E as *mut u8;
/// Timer5 Interrupt Mask Register.
pub const T5IMR: *mut u8 = 0x8F as *mut u8;
/// LF Receiver Calibration Register 1.
pub const LFCALR1: *mut u8 = 0x90 as *mut u8;
/// LF Receiver Calibration Register 2.
pub const LFCALR2: *mut u8 = 0x91 as *mut u8;
/// LF Receiver Calibration Register 3.
pub const LFCALR3: *mut u8 = 0x92 as *mut u8;
/// LF Receiver Calibration Register 4.
pub const LFCALR4: *mut u8 = 0x93 as *mut u8;
/// LF Receiver Calibration Register 5.
pub const LFCALR5: *mut u8 = 0x94 as *mut u8;
/// LF Receiver Calibration Register 6.
pub const LFCALR6: *mut u8 = 0x95 as *mut u8;
/// LF Receiver Calibration Register 7.
pub const LFCALR7: *mut u8 = 0x96 as *mut u8;
/// LF Receiver Calibration Register 8.
pub const LFCALR8: *mut u8 = 0x97 as *mut u8;
/// LF Receiver Calibration Register 9.
pub const LFCALR9: *mut u8 = 0x98 as *mut u8;
/// LF Receiver Calibration Register 10.
pub const LFCALR10: *mut u8 = 0x99 as *mut u8;
/// LF Receiver Calibration Register 11.
pub const LFCALR11: *mut u8 = 0x9A as *mut u8;
/// LF Receiver Calibration Register 12.
pub const LFCALR12: *mut u8 = 0x9B as *mut u8;
/// LF Receiver Calibration Register 13.
pub const LFCALR13: *mut u8 = 0x9C as *mut u8;
/// LF Receiver Calibration Register 14.
pub const LFCALR14: *mut u8 = 0x9D as *mut u8;
/// LF Receiver Calibration Register 15.
pub const LFCALR15: *mut u8 = 0x9E as *mut u8;
/// LF Receiver Calibration Register 16.
pub const LFCALR16: *mut u8 = 0x9F as *mut u8;
/// LF Receiver Calibration Register 17.
pub const LFCALR17: *mut u8 = 0xA0 as *mut u8;
/// LF Receiver Calibration Register 18.
pub const LFCALR18: *mut u8 = 0xA1 as *mut u8;
/// LF Receiver Calibration Register 19.
pub const LFCALR19: *mut u8 = 0xA2 as *mut u8;
/// LF Receiver Calibration Register 20.
pub const LFCALR20: *mut u8 = 0xA3 as *mut u8;
/// LF Receiver Calibration Register 21.
pub const LFCALR21: *mut u8 = 0xA4 as *mut u8;
/// LF Receiver Calibration Register 22.
pub const LFCALR22: *mut u8 = 0xA5 as *mut u8;
/// LF Receiver Calibration Register 23.
pub const LFCALR23: *mut u8 = 0xA6 as *mut u8;
/// LF Receiver Calibration Register 24.
pub const LFCALR24: *mut u8 = 0xA7 as *mut u8;
/// LF Receiver Calibration Register 25.
pub const LFCALR25: *mut u8 = 0xA8 as *mut u8;
/// LF Receiver Calibration Register 26.
pub const LFCALR26: *mut u8 = 0xA9 as *mut u8;
/// LF Receiver Calibration Register 27.
pub const LFCALR27: *mut u8 = 0xAA as *mut u8;
/// LF Receiver Calibration Register 28.
pub const LFCALR28: *mut u8 = 0xAB as *mut u8;
/// LF Receiver Calibration Register 29.
pub const LFCALR29: *mut u8 = 0xAC as *mut u8;
/// LF Receiver Calibration Register 30.
pub const LFCALR30: *mut u8 = 0xAD as *mut u8;
/// LF Receiver Calibration Register 31.
pub const LFCALR31: *mut u8 = 0xAE as *mut u8;
/// LF Receiver Calibration Register 32.
pub const LFCALR32: *mut u8 = 0xAF as *mut u8;
/// LF Receiver Calibration Register 33.
pub const LFCALR33: *mut u8 = 0xB0 as *mut u8;
/// LF Receiver Calibration Register 34.
pub const LFCALR34: *mut u8 = 0xB1 as *mut u8;
/// LF Receiver Calibration Register 35.
pub const LFCALR35: *mut u8 = 0xB2 as *mut u8;
/// LF Receiver Calibration Register 36.
pub const LFCALR36: *mut u8 = 0xB3 as *mut u8;
/// LF Receiver Calibration Register 37.
pub const LFCALR37: *mut u8 = 0xB4 as *mut u8;
/// LF Receiver Calibration Register 38.
pub const LFCALR38: *mut u8 = 0xB5 as *mut u8;
/// LF Receiver Calibration Register 39.
pub const LFCALR39: *mut u8 = 0xB6 as *mut u8;
/// LF Receiver Calibration Register 40.
pub const LFCALR40: *mut u8 = 0xB7 as *mut u8;
/// LF Receiver Calibration Register 41.
pub const LFCALR41: *mut u8 = 0xB8 as *mut u8;
/// LF Receiver Calibration Register 42.
pub const LFCALR42: *mut u8 = 0xB9 as *mut u8;
/// LF Receiver Calibration Register 43.
pub const LFCALR43: *mut u8 = 0xBA as *mut u8;
/// LF Receiver Calibration Register 44.
pub const LFCALR44: *mut u8 = 0xBB as *mut u8;
/// LF Receiver Calibration Register 45.
pub const LFCALR45: *mut u8 = 0xBC as *mut u8;
/// LF Receiver Calibration Register 46.
pub const LFCALR46: *mut u8 = 0xBD as *mut u8;
/// LF Receiver Calibration Register 47.
pub const LFCALR47: *mut u8 = 0xBE as *mut u8;
/// LF Receiver Calibration Register 48.
pub const LFCALR48: *mut u8 = 0xBF as *mut u8;
/// LF Receiver Calibration Register 49.
pub const LFCALR49: *mut u8 = 0xC0 as *mut u8;
/// LF Receiver Calibration Register 50.
pub const LFCALR50: *mut u8 = 0xC1 as *mut u8;
/// LF Receiver Calibration Register 51.
pub const LFCALR51: *mut u8 = 0xC2 as *mut u8;
/// LF Receiver Calibration Register 52.
pub const LFCALR52: *mut u8 = 0xC3 as *mut u8;
/// LF Receiver Calibration Register 53.
pub const LFCALR53: *mut u8 = 0xC4 as *mut u8;
pub const XFUSE: *mut u8 = 0xC5 as *mut u8;
/// Middle RC oscillator calibration Register.
pub const MRCCAL: *mut u8 = 0xC6 as *mut u8;
/// Fast RC oscillator calibration Register.
pub const FRCCAL: *mut u8 = 0xC7 as *mut u8;
/// RC oscillator Temperature Compensation register.
pub const RCTCAL: *mut u8 = 0xC8 as *mut u8;
/// Clock management status Register.
pub const CMSR: *mut u8 = 0xC9 as *mut u8;
/// Clock management override control register.
pub const CMOCR: *mut u8 = 0xCA as *mut u8;
/// Supply Interrupt Flag Register.
pub const SUPFR: *mut u8 = 0xCB as *mut u8;
/// Supply Control Register.
pub const SUPCR: *mut u8 = 0xCC as *mut u8;
/// Supply calibration register 1.
pub const SUPCA1: *mut u8 = 0xCD as *mut u8;
/// Supply calibration register 2.
pub const SUPCA2: *mut u8 = 0xCE as *mut u8;
/// Supply calibration register 3.
pub const SUPCA3: *mut u8 = 0xCF as *mut u8;
/// Supply calibration register 4.
pub const SUPCA4: *mut u8 = 0xD0 as *mut u8;
/// Calibration ready signature.
pub const CALRDY: *mut u8 = 0xD1 as *mut u8;
/// Data FIFO Status Register.
pub const DFS: *mut u8 = 0xD2 as *mut u8;
/// Data FIFO Fill Level Register.
pub const DFL: *mut u8 = 0xD5 as *mut u8;
/// Data FIFO Write Pointer.
pub const DFWP: *mut u8 = 0xD6 as *mut u8;
/// Data FIFO Read Pointer.
pub const DFRP: *mut u8 = 0xD7 as *mut u8;
/// Data FIFO Data Register.
pub const DFD: *mut u8 = 0xD8 as *mut u8;
/// Data FIFO Interrupt Mask Register.
pub const DFI: *mut u8 = 0xD9 as *mut u8;
/// Data FIFO Configuration Register.
pub const DFC: *mut u8 = 0xDA as *mut u8;
/// Support FIFO Status Register.
pub const SFS: *mut u8 = 0xDB as *mut u8;
/// Support FIFO Fill Level Register.
pub const SFL: *mut u8 = 0xDC as *mut u8;
/// Support FIFO Write Pointer.
pub const SFWP: *mut u8 = 0xDD as *mut u8;
/// Support FIFO Read Pointer.
pub const SFRP: *mut u8 = 0xDE as *mut u8;
/// Support FIFO Data Register.
pub const SFD: *mut u8 = 0xDF as *mut u8;
/// Support FIFO Interrupt Mask Register.
pub const SFI: *mut u8 = 0xE0 as *mut u8;
/// Support FIFO Configuration Register.
pub const SFC: *mut u8 = 0xE1 as *mut u8;
/// SSM Control Register.
pub const SSMCR: *mut u8 = 0xE2 as *mut u8;
/// General Timer/Counter Control Register.
pub const GTCCR: *mut u8 = 0xE3 as *mut u8;
/// SSM Filter Bandwidth Register.
pub const SSMFBR: *mut u8 = 0xE4 as *mut u8;
/// SSM Run Register.
pub const SSMRR: *mut u8 = 0xE5 as *mut u8;
/// SSM Status Register.
pub const SSMSR: *mut u8 = 0xE6 as *mut u8;
/// SSM Interrupt Flag Register.
pub const SSMIFR: *mut u8 = 0xE7 as *mut u8;
/// SSM interrupt mask register.
pub const SSMIMR: *mut u8 = 0xE8 as *mut u8;
/// Master State Machine state register.
pub const MSMSTR: *mut u8 = 0xE9 as *mut u8;
/// SSM State Register.
pub const SSMSTR: *mut u8 = 0xEA as *mut u8;
/// VX Mode Control Register.
pub const VXMCTRL: *mut u8 = 0xEB as *mut u8;
/// Master State Machine Control Register 1.
pub const MSMCR1: *mut u8 = 0xEC as *mut u8;
/// Master State Machine Control Register 2.
pub const MSMCR2: *mut u8 = 0xED as *mut u8;
/// Master State Machine Control Register 3.
pub const MSMCR3: *mut u8 = 0xEE as *mut u8;
/// Master State Machine Control Register 4.
pub const MSMCR4: *mut u8 = 0xEF as *mut u8;
/// SPI2 control Register.
pub const SP2CR: *mut u8 = 0xF7 as *mut u8;
/// SPI2 Data Register.
pub const SP2DR: *mut u8 = 0xF8 as *mut u8;
/// SPI2 Status Register.
pub const SP2SR: *mut u8 = 0xF9 as *mut u8;
/// Trace ID Register.
pub const TRCID: *mut u16 = 0xFC as *mut u16;
/// Trace ID Register low byte.
pub const TRCIDL: *mut u8 = 0xFC as *mut u8;
/// Trace ID Register high byte.
pub const TRCIDH: *mut u8 = 0xFD as *mut u8;
/// Trace Data Register.
pub const TRCDR: *mut u8 = 0xFF as *mut u8;
/// Front-End Status Register.
pub const FESR: *mut u8 = 0x100 as *mut u8;
/// Front-End Enable Register 1.
pub const FEEN1: *mut u8 = 0x101 as *mut u8;
/// Front-End Enable Register 2.
pub const FEEN2: *mut u8 = 0x102 as *mut u8;
/// Reserved.
pub const FELNA: *mut u8 = 0x103 as *mut u8;
/// Front-End Antenna Tuning.
pub const FEAT: *mut u8 = 0x104 as *mut u8;
/// Front-End Power Amplifier Control Register.
pub const FEPAC: *mut u8 = 0x105 as *mut u8;
/// Front-End VCO Tuning Register.
pub const FEVCT: *mut u8 = 0x106 as *mut u8;
/// Front-End RC Tuning Register.
pub const FEBT: *mut u8 = 0x107 as *mut u8;
/// Front-End Main and Swallow Control Register.
pub const FEMS: *mut u8 = 0x108 as *mut u8;
/// Front-End RC Tuning 4bit Register.
pub const FETN4: *mut u8 = 0x109 as *mut u8;
/// Front-End Control Register.
pub const FECR: *mut u8 = 0x10A as *mut u8;
/// Front-End VCO and PLL control.
pub const FEVCO: *mut u8 = 0x10B as *mut u8;
/// Front-End Antenna Level Detector Range.
pub const FEALR: *mut u8 = 0x10C as *mut u8;
/// Front-End Antenna.
pub const FEANT: *mut u8 = 0x10D as *mut u8;
/// Reserved.
pub const FEBIA: *mut u8 = 0x10E as *mut u8;
/// Clock output divider settings Register.
pub const CLKOD: *mut u8 = 0x115 as *mut u8;
/// Clock output control Register.
pub const CLKOCR: *mut u8 = 0x116 as *mut u8;
/// Front-End Test Enable Register 1.
pub const FETE1: *mut u8 = 0x11C as *mut u8;
/// Front-End Test Enable Register 2.
pub const FETE2: *mut u8 = 0x11D as *mut u8;
/// Front-End Test Enable Register 3.
pub const FETE3: *mut u8 = 0x11E as *mut u8;
/// Front-End Test Data Register.
pub const FETD: *mut u8 = 0x11F as *mut u8;
/// Tx Modulator Finite State Machine.
pub const TMFSM: *mut u8 = 0x120 as *mut u8;
/// Tx Modulator CRC Result low byte.
pub const TMCRCL: *mut u8 = 0x121 as *mut u8;
/// Tx Modulator CRC Result.
pub const TMCRC: *mut u16 = 0x121 as *mut u16;
/// Tx Modulator CRC Result high byte.
pub const TMCRCH: *mut u8 = 0x122 as *mut u8;
/// Tx Modulator CRC Skip Bit Number.
pub const TMCSB: *mut u8 = 0x123 as *mut u8;
/// Tx Modulator CRC Init Value.
pub const TMCI: *mut u16 = 0x124 as *mut u16;
/// Tx Modulator CRC Init Value low byte.
pub const TMCIL: *mut u8 = 0x124 as *mut u8;
/// Tx Modulator CRC Init Value high byte.
pub const TMCIH: *mut u8 = 0x125 as *mut u8;
/// Tx Modulator CRC Polynomial low byte.
pub const TMCPL: *mut u8 = 0x126 as *mut u8;
/// Tx Modulator CRC Polynomial.
pub const TMCP: *mut u16 = 0x126 as *mut u16;
/// Tx Modulator CRC Polynomial high byte.
pub const TMCPH: *mut u8 = 0x127 as *mut u8;
/// Tx Modulator Shift Register.
pub const TMSHR: *mut u8 = 0x128 as *mut u8;
/// Tx Modulator Telegram Length Register.
pub const TMTLL: *mut u16 = 0x129 as *mut u16;
/// Tx Modulator Telegram Length Register low byte.
pub const TMTLLL: *mut u8 = 0x129 as *mut u8;
/// Tx Modulator Telegram Length Register high byte.
pub const TMTLLH: *mut u8 = 0x12A as *mut u8;
/// Tx Modulator Stop Sequence Configuration.
pub const TMSSC: *mut u8 = 0x12B as *mut u8;
/// Tx Modulator Status Register.
pub const TMSR: *mut u8 = 0x12C as *mut u8;
/// Tx Modulator Control Register 2.
pub const TMCR2: *mut u8 = 0x12D as *mut u8;
/// Tx Modulator Control Register 1.
pub const TMCR1: *mut u8 = 0x12E as *mut u8;
/// LF Receiver Decoder Setting Register 1.
pub const LFDSR1: *mut u8 = 0x130 as *mut u8;
/// LF Receiver Decoder Setting Register 2.
pub const LFDSR2: *mut u8 = 0x131 as *mut u8;
/// LF Receiver Decoder Setting Register 3.
pub const LFDSR3: *mut u8 = 0x132 as *mut u8;
/// LF Receiver Decoder Setting Register 4.
pub const LFDSR4: *mut u8 = 0x133 as *mut u8;
/// LF Decoder Setting 5 Register.
pub const LFDSR5: *mut u8 = 0x134 as *mut u8;
/// LF Decoder Setting 6 Register.
pub const LFDSR6: *mut u8 = 0x135 as *mut u8;
/// LF Decoder Setting 7 Register.
pub const LFDSR7: *mut u8 = 0x136 as *mut u8;
/// LF Decoder Setting 8 Register.
pub const LFDSR8: *mut u8 = 0x137 as *mut u8;
/// LF Decoder Setting 9 Register.
pub const LFDSR9: *mut u8 = 0x138 as *mut u8;
/// LF Decoder Setting 10 Register.
pub const LFDSR10: *mut u8 = 0x139 as *mut u8;
/// Low Frequency Decoder Setting Register 11.
pub const LFDSR11: *mut u8 = 0x13A as *mut u8;
/// EEPROM Protection Register 1.
pub const EEPR1: *mut u8 = 0x13B as *mut u8;
/// EEPROM Protection Register 2.
pub const EEPR2: *mut u8 = 0x13C as *mut u8;
/// EEPROM Protection Register 3.
pub const EEPR3: *mut u8 = 0x13D as *mut u8;
/// CRC Control Register.
pub const CRCCR: *mut u8 = 0x145 as *mut u8;
/// CRC Data Output Register.
pub const CRCDOR: *mut u8 = 0x146 as *mut u8;
/// LF Receiver SRC Tuning MSB.
pub const LFSRCTM: *mut u8 = 0x151 as *mut u8;
/// DeBounce Control Register.
pub const DBCR: *mut u8 = 0x152 as *mut u8;
/// Debounce Timer Compare Register.
pub const DBTC: *mut u8 = 0x153 as *mut u8;
/// DeBounce Enable Port B.
pub const DBENB: *mut u8 = 0x154 as *mut u8;
/// DeBounce Enable Port C.
pub const DBENC: *mut u8 = 0x155 as *mut u8;
/// Debugging Support Switch.
pub const DBGSW: *mut u8 = 0x156 as *mut u8;
/// SPI FIFO Fill Status Register.
pub const SFFR: *mut u8 = 0x157 as *mut u8;
/// SPI FIFO Interrupt Register.
pub const SFIR: *mut u8 = 0x158 as *mut u8;
/// Timer2 Interrupt Flag Register.
pub const T2IFR: *mut u8 = 0x159 as *mut u8;
/// Program Memory Status Register.
pub const PGMST: *mut u8 = 0x15A as *mut u8;
/// EEPROM Status Register.
pub const EEST: *mut u8 = 0x15B as *mut u8;
/// LF Receiver SRC Tuning LSB.
pub const LFSRCTL: *mut u8 = 0x15C as *mut u8;
/// Pin change Interrupt flag Register.
pub const PCIFR: *mut u8 = 0x161 as *mut u8;
/// Timer0 Control Register.
pub const T0CR: *mut u8 = 0x162 as *mut u8;
/// DeBounce Enable Port D.
pub const DBEND: *mut u8 = 0x164 as *mut u8;
/// Transponder Control Register 1.
pub const TPCR1: *mut u8 = 0x165 as *mut u8;
/// Transponder Interrupt Mask Register.
pub const TPIMR: *mut u8 = 0x166 as *mut u8;
/// Transponder Decoder Comparator Register 1.
pub const TPDCR1: *mut u8 = 0x167 as *mut u8;
/// Transponder Decoder Comparator Register 2.
pub const TPDCR2: *mut u8 = 0x168 as *mut u8;
/// Transponder Decoder Comparator Register 3.
pub const TPDCR3: *mut u8 = 0x169 as *mut u8;
/// Transponder Decoder Comparator Register 4.
pub const TPDCR4: *mut u8 = 0x16A as *mut u8;
/// Transponder Decoder Comparator Register 5.
pub const TPDCR5: *mut u8 = 0x16B as *mut u8;
/// Transponder Encoder Comparator Register 1.
pub const TPECR1: *mut u8 = 0x16C as *mut u8;
/// Transponder Encoder Comparator Register 2.
pub const TPECR2: *mut u8 = 0x16D as *mut u8;
/// Transponder Encoder Comparator Register 3.
pub const TPECR3: *mut u8 = 0x16E as *mut u8;
/// Transponder Encoder Comparator Register 4.
pub const TPECR4: *mut u8 = 0x16F as *mut u8;
/// Transponder Encoder Mode Register.
pub const TPECMR: *mut u8 = 0x170 as *mut u8;
/// Transponder Control Register 3.
pub const TPCR3: *mut u8 = 0x171 as *mut u8;
/// Transponder Control Register 4.
pub const TPCR4: *mut u8 = 0x172 as *mut u8;
/// Transponder Control Register 5.
pub const TPCR5: *mut u8 = 0x173 as *mut u8;
/// Transponder Calibration Register 1.
pub const TPCALR1: *mut u8 = 0x175 as *mut u8;
/// Transponder Calibration Register 2.
pub const TPCALR2: *mut u8 = 0x176 as *mut u8;
/// Transponder Calibration Register 3.
pub const TPCALR3: *mut u8 = 0x177 as *mut u8;
/// Transponder Calibration Register 4.
pub const TPCALR4: *mut u8 = 0x178 as *mut u8;
/// Transponder Calibration Register 5.
pub const TPCALR5: *mut u8 = 0x179 as *mut u8;
/// Transponder Calibration Register 6.
pub const TPCALR6: *mut u8 = 0x17A as *mut u8;
/// Transponder Calibration Register 7.
pub const TPCALR7: *mut u8 = 0x17B as *mut u8;
/// Transponder Calibration Register 8.
pub const TPCALR8: *mut u8 = 0x17C as *mut u8;
/// Transponder Calibration Register 9.
pub const TPCALR9: *mut u8 = 0x17D as *mut u8;
/// Transponder Calibration Register 10.
pub const TPCALR10: *mut u8 = 0x17E as *mut u8;
/// AES Data Pointer Register.
pub const AESDPR: *mut u8 = 0x17F as *mut u8;
/// AES Key Register.
pub const AESKR: *mut u8 = 0x180 as *mut u8;
/// AES Data Register.
pub const AESDR: *mut u8 = 0x181 as *mut u8;
/// General Purpose I/O Register 3.
pub const GPIOR3: *mut u8 = 0x182 as *mut u8;
/// General Purpose I/O Register 4.
pub const GPIOR4: *mut u8 = 0x183 as *mut u8;
/// General Purpose I/O Register 5.
pub const GPIOR5: *mut u8 = 0x184 as *mut u8;
/// General Purpose I/O Register 6.
pub const GPIOR6: *mut u8 = 0x185 as *mut u8;
/// General Purpose I/O Register 7.
pub const GPIOR7: *mut u8 = 0x186 as *mut u8;
/// General Purpose I/O Register 8.
pub const GPIOR8: *mut u8 = 0x187 as *mut u8;
/// Protocol Handler Bit Counter Read Register.
pub const PHBCRR: *mut u8 = 0x188 as *mut u8;
/// LF Receiver Calibration Protect Register.
pub const LFCPR: *mut u8 = 0x18E as *mut u8;
/// LF Receiver Interrupt Mask Register.
pub const LFIMR: *mut u8 = 0x18F as *mut u8;
/// PH ID0 Register.
pub const PHID0: *mut u16 = 0x190 as *mut u16;
/// PH Identifier 0 Length Register.
pub const PHID0L: *mut u8 = 0x194 as *mut u8;
/// PH ID1 Register.
pub const PHID1: *mut u16 = 0x195 as *mut u16;
/// PH Identifier 1 Length Register.
pub const PHID1L: *mut u8 = 0x199 as *mut u8;
/// Protocol Handler ID Frame Register.
pub const PHIDFR: *mut u8 = 0x19A as *mut u8;
/// LF Receiver Synchronization Symbols Register.
pub const LFSYSY: *mut u16 = 0x19B as *mut u16;
/// LF Receiver Synchronization Length Register.
pub const LFSYLE: *mut u8 = 0x19F as *mut u8;
/// LF Receiver Stop Bit Register.
pub const LFSTOP: *mut u8 = 0x1A0 as *mut u8;
/// LF Timer Compare Register.
pub const LTCOR: *mut u8 = 0x1A1 as *mut u8;
/// Timer1 Interrupt Flag Register.
pub const T1IFR: *mut u8 = 0x1A2 as *mut u8;
/// Protocol Handler Telegram Bit Length Register.
pub const PHTBLR: *mut u8 = 0x1A4 as *mut u8;
/// Protocol Handler Data Frame end Register.
pub const PHDFR: *mut u8 = 0x1A5 as *mut u8;
/// LF Timer Event Mask Register.
pub const LTEMR: *mut u8 = 0x1A6 as *mut u8;
/// LF Receiver Channel 3 Quality Faktor Register.
pub const LFQC3: *mut u8 = 0x1A7 as *mut u8;
/// LF Receiver Channel 2 Quality Faktor Register.
pub const LFQC2: *mut u8 = 0x1A8 as *mut u8;
/// LF Receiver Channel 1 Quality Faktor Register.
pub const LFQC1: *mut u8 = 0x1A9 as *mut u8;
/// TWI2 Bit Rate Register.
pub const TW2BR: *mut u8 = 0x1AA as *mut u8;
/// TWI2 Control Register.
pub const TW2CR: *mut u8 = 0x1AB as *mut u8;
/// TWI2 Status Register.
pub const TW2SR: *mut u8 = 0x1AC as *mut u8;
/// TWI2 Data Register.
pub const TW2DR: *mut u8 = 0x1AD as *mut u8;
/// TWI2 (Slave) Address Register.
pub const TW2AR: *mut u8 = 0x1AE as *mut u8;
/// TWI2 Address Mask Register.
pub const TW2AMR: *mut u8 = 0x1AF as *mut u8;
/// RSSI Control Register.
pub const RSCR: *mut u8 = 0x1B0 as *mut u8;
/// RSSI Status Register.
pub const RSSR: *mut u8 = 0x1B1 as *mut u8;
/// RSSI Measurement Setting 1 Register.
pub const RSMS1R: *mut u8 = 0x1B2 as *mut u8;
/// RSSI Measurement Setting 2 Register.
pub const RSMS2R: *mut u8 = 0x1B3 as *mut u8;
/// RSSI Flag Register.
pub const RSFR: *mut u8 = 0x1B4 as *mut u8;
/// RSSI Calibration Register.
pub const RSCALIB: *mut u8 = 0x1B6 as *mut u8;
/// RSSI Delay Register.
pub const RSDLYR: *mut u8 = 0x1B7 as *mut u8;
/// RSSI Result 1 Low Byte Register.
pub const RSRES1L: *mut u8 = 0x1B8 as *mut u8;
/// RSSI Result 1 High Byte Register.
pub const RSRES1H: *mut u8 = 0x1B9 as *mut u8;
/// RSSI Result 2 Low Byte Register.
pub const RSRES2L: *mut u8 = 0x1BA as *mut u8;
/// RSSI Result 2 High Byte Register.
pub const RSRES2H: *mut u8 = 0x1BB as *mut u8;
/// RSSI Result 3 Low Byte Register.
pub const RSRES3L: *mut u8 = 0x1BC as *mut u8;
/// RSSI Result 3 High Byte Register.
pub const RSRES3H: *mut u8 = 0x1BD as *mut u8;
/// RSSI Result 4 Low Byte Register.
pub const RSRES4L: *mut u8 = 0x1BE as *mut u8;
/// RSSI Result 4 High Byte Register.
pub const RSRES4H: *mut u8 = 0x1BF as *mut u8;
/// RSSI SRC Calibration Register.
pub const RSSRCR: *mut u8 = 0x1C0 as *mut u8;
/// Sign Detection Channel 1 vs 2 Result Register.
pub const SD12RR: *mut u8 = 0x1C1 as *mut u8;
/// Sign Detection Channel 1 vs 3 Result Register.
pub const SD13RR: *mut u8 = 0x1C2 as *mut u8;
/// Sign Detection Channel 2 vs 3 Result Register.
pub const SD23RR: *mut u8 = 0x1C3 as *mut u8;
/// Sign Detection 360 Degree Result Register.
pub const SD360R: *mut u8 = 0x1C4 as *mut u8;
/// RSSI Debug Register.
pub const RSDBGR: *mut u8 = 0x1C5 as *mut u8;
/// LF Data FIFO Status Register.
pub const LDFS: *mut u8 = 0x1D1 as *mut u8;
/// Timer4 interrupt flag Register.
pub const T4IFR: *mut u8 = 0x1D2 as *mut u8;
/// LF Data FIFO Write Pointer.
pub const LDFWP: *mut u8 = 0x1D3 as *mut u8;
/// LF Data FIFO Read Pointer.
pub const LDFRP: *mut u8 = 0x1D4 as *mut u8;
/// Timer5 Interrupt Flag Register.
pub const T5IFR: *mut u8 = 0x1D5 as *mut u8;
/// LF Data FIFO Interrupt Mask Register.
pub const LDFIM: *mut u8 = 0x1D6 as *mut u8;
/// LF Data FIFO Configuration Register.
pub const LDFC: *mut u8 = 0x1D7 as *mut u8;
/// Protocol Handler Interrupt Mask Register.
pub const PHIMR: *mut u8 = 0x1D8 as *mut u8;
/// Protocol Handler CRC Control Register.
pub const PHCRCR: *mut u8 = 0x1D9 as *mut u8;
/// PH CRC Start Value Register low byte.
pub const PHCSTL: *mut u8 = 0x1DA as *mut u8;
/// PH CRC Start Value Register.
pub const PHCST: *mut u16 = 0x1DA as *mut u16;
/// PH CRC Start Value Register high byte.
pub const PHCSTH: *mut u8 = 0x1DB as *mut u8;
/// PH CRC Polynomial Register.
pub const PHCRP: *mut u16 = 0x1DC as *mut u16;
/// PH CRC Polynomial Register low byte.
pub const PHCRPL: *mut u8 = 0x1DC as *mut u8;
/// PH CRC Polynomial Register high byte.
pub const PHCRPH: *mut u8 = 0x1DD as *mut u8;
/// PH CRC Checksum Register low byte.
pub const PHCSRL: *mut u8 = 0x1DE as *mut u8;
/// PH CRC Checksum Register.
pub const PHCSR: *mut u16 = 0x1DE as *mut u16;
/// PH CRC Checksum Register high byte.
pub const PHCSRH: *mut u8 = 0x1DF as *mut u8;
/// CRC Data Input Register.
pub const CRCDIR: *mut u8 = 0x1E0 as *mut u8;
/// Timer3 interrupt flag Register.
pub const T3IFR: *mut u8 = 0x1E1 as *mut u8;
/// Clock Management Control Register.
pub const CMCR: *mut u8 = 0x1E3 as *mut u8;
/// Clock interrupt mask Register.
pub const CMIMR: *mut u8 = 0x1E4 as *mut u8;
/// Clock Prescaler Register.
pub const CLPR: *mut u8 = 0x1E5 as *mut u8;
/// Voltage Monitor Control Register.
pub const VMCR: *mut u8 = 0x1E6 as *mut u8;
/// Downbond Test Register.
pub const DBONDR: *mut u8 = 0x1E7 as *mut u8;
/// Calibration ready signature LFVCC.
pub const CALRDYLF: *mut u8 = 0x1E8 as *mut u8;
/// TWI1 Bit Rate Register.
pub const TW1BR: *mut u8 = 0x1E9 as *mut u8;
/// TWI1 Control Register.
pub const TW1CR: *mut u8 = 0x1EA as *mut u8;
/// TWI1 Status Register.
pub const TW1SR: *mut u8 = 0x1EB as *mut u8;
/// TWI1 Data Register.
pub const TW1DR: *mut u8 = 0x1EC as *mut u8;
/// TWI1 (Slave) Address Register.
pub const TW1AR: *mut u8 = 0x1ED as *mut u8;
/// TWI1 Address Mask Register.
pub const TW1AMR: *mut u8 = 0x1EE as *mut u8;
/// Pad Driver Strength Control Register.
pub const PDSCR: *mut u8 = 0x1EF as *mut u8;
/// Timer Modulator Output Control Register.
pub const TMOCR: *mut u8 = 0x1F0 as *mut u8;
/// Slow RC oscillator calibration.
pub const SRCCAL: *mut u8 = 0x1F1 as *mut u8;
/// SRC oscillator Temperature Compensation register.
pub const SRCTCAL: *mut u8 = 0x1F2 as *mut u8;
/// Supply calibration register 5.
pub const SUPCA5: *mut u8 = 0x1F3 as *mut u8;
/// Supply calibration register 6.
pub const SUPCA6: *mut u8 = 0x1F4 as *mut u8;
/// Supply calibration register 7.
pub const SUPCA7: *mut u8 = 0x1F5 as *mut u8;
/// Supply calibration register 8.
pub const SUPCA8: *mut u8 = 0x1F6 as *mut u8;
/// Supply calibration register 9.
pub const SUPCA9: *mut u8 = 0x1F7 as *mut u8;
/// Supply calibration register 10.
pub const SUPCA10: *mut u8 = 0x1F8 as *mut u8;
/// Transponder Calibration Register 11.
pub const TPCALR11: *mut u8 = 0x1F9 as *mut u8;
/// Transponder Calibration Register 12.
pub const TPCALR12: *mut u8 = 0x1FA as *mut u8;
/// Transponder Calibration Register 13.
pub const TPCALR13: *mut u8 = 0x1FB as *mut u8;
/// Power Management Test Enable Register.
pub const PMTER: *mut u8 = 0x1FE as *mut u8;
/// Slow RC oscillator calibration LSB.
pub const SRCCALL: *mut u8 = 0x1FF as *mut u8;