Module avrd::ata5787
[−]
[src]
The AVR ATA5787 microcontroller
Variants
Pinout | Package | Operating temperature | Operating voltage | Max speed | |
---|---|---|---|---|---|
standard | 0°C - 0°C | 2.4V - 5.5V | 0 MHz |
Registers by module (not exhaustive)
EEPROM modules
- EEPROM
INT modules
- INT
Constants
CALRDY |
Calibration Ready Signature. |
CHCR |
Channel Filter Configuration Register. |
CHDN |
Channel Filter Down Sampling Register. |
CLKOCR |
Clock output control Register. |
CLKOD |
Clock Output Divider. |
CLPR |
Clock Prescaler. |
CMCR |
Clock Management Control Register. |
CMIMR |
Clock Management Interrupt Mask Register. |
CMOCR |
Clock Management Override Control Register. |
CMSR |
Clock Management Status Register. |
CRCCR |
CRC Control Register. |
CRCDIR |
CRC Data Input Register. |
CRCDOR |
CRC Data Output Register. |
DBCR |
Debounce Control Register. |
DBENB |
Debounce Enable Port B. |
DBENC |
Debounce Enable Port C. |
DBGSW |
Debug Support Switch. |
DBTC |
Debounce Timer Compare. |
DCC1 |
DCDC Converter Control 1. |
DCC2 |
DCDC Converter Control 2. |
DCCAL1 |
DCDC Converter Calibration 1. |
DCCAL2 |
DCDC Converter Calibration 2. |
DCCAL3 |
DCDC Converter Calibration 3. |
DCTST |
DCDC Converter Test Mode. |
DDRB |
Port B Data Direction. |
DDRC |
Port C Data Direction. |
DFC |
Data FIFO Configuration. |
DFD |
Data FIFO Data. |
DFI |
Data FIFO Interrupt Mask. |
DFL |
Data FIFO Fill Level. |
DFRP |
Data FIFO Read Pointer. |
DFS |
Data FIFO Status. |
DFTL |
Data FIFO Telegram Length. |
DFTLH |
Data FIFO Telegram Length high byte. |
DFTLL |
Data FIFO Telegram Length low byte. |
DFWP |
Data FIFO Write Pointer. |
DMCDA |
Demodulator Carrier Detect Path A. |
DMCDB |
Demodulator Carrier Detect Path B. |
DMCRA |
Demodulator Control Path A. |
DMCRB |
Demodulator Control Path B. |
DMDN |
Demodulator Down Sampling. |
DMMA |
Demodulator Mode Path A. |
DMMB |
Demodulator Mode Path B. |
DMPATA |
Demodulator Signal Check Pattern Path A. |
DMPATB |
Demodulator Signal Check Pattern Path B. |
DMPC |
Demodulator Pattern Check Control. |
DMPCA |
Demodulator Pattern Check Control Path A. |
DMPCB |
Demodulator Pattern Check Control Path B. |
DMSRA |
Demodulator Symbol Rate Path A. |
DMSRB |
Demodulator Symbol Rate Path B. |
DWDR |
Debug Wire Data Register. |
EEAR |
EEPROM Address Register. |
EEARH |
EEPROM Address Register high byte. |
EEARL |
EEPROM Address Register low byte. |
EECR |
EEPROM Control Register. |
EECR2 |
EEPROM Control Register 2. |
EEDR |
EEPROM Data Register. |
EEPR |
EEPROM Protect Register. |
EEST |
EEPROM Status Register. |
EICRA |
External Interrupt Control Register A. |
EIFR |
External Interrupt Flag Register. |
EIMSK |
External Interrupt Mask. |
EOTC1A |
End Of Telegram Conditions 1 Path A. |
EOTC1B |
End Of Telegram Conditions 1 Path B. |
EOTC2A |
End Of Telegram Conditions 2 Path A. |
EOTC2B |
End Of Telegram Conditions 2 Path B. |
EOTC3A |
End Of Telegram Conditions 3 Path A. |
EOTC3B |
End Of Telegram Conditions 3 Path B. |
EOTCA |
End Of Telegram Conditions Path A. |
EOTCB |
End Of Telegram Conditions Path B. |
EOTSA |
End Of Telegram Status Path A. |
EOTSB |
End Of Telegram Status Path B. |
FEAS |
RF Front End Antenna Switch. |
FEBIA |
RF Front End Amplifier Bias. |
FEBT |
RF Front End RC Tuning. |
FECR |
RF Front End Control Register. |
FEEN1 |
RF Front End Enable 1. |
FEEN2 |
RF Front End Enable 2. |
FELNA |
RF Front End LNA Bias. |
FEMS |
RF Front End Main and Swallow Counter. |
FESR |
RF Front End Status Register. |
FETN4 |
RF Front End RC Tuning 4bit Register. |
FEVCO |
RF Front End VCO and PLL Control. |
FEVCT |
RF Front End VCO Tuning. |
FFREQ1H |
Fractional Frequency 1 High Byte. |
FFREQ1L |
Fractional Frequency 1 Low Byte. |
FFREQ1M |
Fractional Frequency 1 Middle Byte. |
FFREQ2H |
Fractional Frequency 2 High Byte. |
FFREQ2L |
Fractional Frequency 2 Low Byte. |
FFREQ2M |
Fractional Frequency 2 Middle Byte. |
FRCCAL |
Fast RC Oscillator Calibration. |
FSEN |
Frequency Synthesizer Enable. |
GPIOR0 |
General Purpose I/O Register 0. |
GPIOR1 |
General Purpose I/O Register 1. |
GPIOR2 |
General Purpose I/O Register 2. |
GPIOR3 |
General Purpose I/O Register 3. |
GPIOR4 |
General Purpose I/O Register 4. |
GPIOR5 |
General Purpose I/O Register 5. |
GPIOR6 |
General Purpose I/O Register 6. |
GTCCR |
General Timer/Counter Control Register. |
GTCR |
Get Telegram Control Register. |
IDB0 |
ID Check Byte 0. |
IDB1 |
ID Check Byte 1. |
IDB2 |
ID Check Byte 2. |
IDB3 |
ID Check Byte 3. |
IDC |
ID Check Configuration. |
IDS |
ID Check Status. |
LINBRRH |
LIN/UART Baud Rate Register High Byte. |
LINBRRL |
LIN/UART Baud Rate Register Low Byte. |
LINBTR |
LIN/UART Bit Timing Register. |
LINCR |
LIN/UART Control Register. |
LINDAT |
LIN/UART Data Register. |
LINDLR |
LIN/UART Data Length Register. |
LINENIR |
LIN/UART Enable Interrupt Register. |
LINERR |
LIN/UART Error Register. |
LINIDR |
LIN/UART Identifier Register. |
LINSEL |
LIN/UART Data Buffer Selection. |
LINSIR |
LIN Status and Interrupt Register. |
LOCKBIT | |
LOW | |
MCUCR |
MCU Control Register. |
MCUSR |
MCU Status Register. |
MSMCR1 |
Master State Machine Control Register 1. |
MSMCR2 |
Master State Machine Control Register 2. |
MSMCR3 |
Master State Machine Control Register 3. |
MSMCR4 |
Master State Machine Control Register 4. |
MSMSTR |
Master State Machine State Register. |
OCCNT |
Oscillator Calibration Counter Value. |
OCCR |
Oscillator Calibration Counter Configuration Register. |
OCGATE |
Oscillator Calibration Counter Gate. |
PCICR |
Pin Change Interrupt Control Register. |
PCIFR |
Pin Change Interrupt Flag Register. |
PCMSK0 |
Pin Change Mask Register 0. |
PCMSK1 |
Pin Change Mask Register 1. |
PGMST |
Program Memory Status Register. |
PINB |
Port B Input Pins. |
PINC |
Port C Input Pins. |
PORTB |
Port B Data Register. |
PORTC |
Port C Data Register. |
PRR0 |
Power Reduction Register 0. |
PRR1 |
Power Reduction Register 1. |
PRR2 |
Power Reduction Register 2. |
RCTUNE4 |
Resistor Capacitor 4 Bit Tuning. |
RDCR |
Rx DSP Control Register. |
RDOCR |
Rx DSP Output Control. |
RDPR |
Rx DSP Power Reduction. |
RDSIFR |
Rx DSP Status Interrupt Flag Register. |
RDSIMR |
Rx DSP Status Interrupt Mask Register. |
RSCOM |
RSSI Compensation Register. |
RSHDV |
RSSI High Band Damping Value. |
RSHSG |
RSSI LNA High Sensitivity Gain. |
RSIFG |
RSSI IF Amplifier Gain. |
RSLDV |
RSSI Low Band Damping Value. |
RSSAV |
RSSI Average Value. |
RSSC |
RSSI Configuration Register. |
RSSH |
RSSI High Threshold. |
RSSL |
RSSI Low Threshold. |
RSSPK |
RSSI Peak Value. |
RXBC1 |
Rx Buffer Configuration 1. |
RXBC2 |
Rx Buffer Configuration 2. |
RXCIHA |
Rx CRC Init Value High Byte Path A. |
RXCIHB |
Rx CRC Init Value High Byte Path B. |
RXCILA |
Rx CRC Init Value Low Byte Path A. |
RXCILB |
Rx CRC Init Value Low Byte Path B. |
RXCPHA |
Rx CRC Polynomial High Byte Path A. |
RXCPHB |
Rx CRC Polynomial High Byte Path B. |
RXCPLA |
Rx CRC Polynomial Low Byte Path A. |
RXCPLB |
Rx CRC Polynomial Low Byte Path B. |
RXCRHA |
Rx CRC Result High Byte Path A. |
RXCRHB |
Rx CRC Result High Byte Path B. |
RXCRLA |
Rx CRC Result Low Byte Path A. |
RXCRLB |
Rx CRC Result Low Byte Path B. |
RXCSBA |
Rx CRC Skip Bit Number Path A. |
RXCSBB |
Rx CRC Skip Bit Number Path B. |
RXDSA |
Receive Data Shift Register Path A. |
RXDSB |
Receive Data Shift Register Path B. |
RXFOA |
Received Frequency Offset vs Intermediate Frequency Path A. |
RXFOB |
Received Frequency Offset vs Intermediate Frequency Path B. |
RXTLHA |
Rx Telegram Length High Byte Path A. |
RXTLHB |
Rx Telegram Length High Byte Path B. |
RXTLLA |
Rx Telegram Length Low Byte Path A. |
RXTLLB |
Rx Telegram Length Low Byte Path B. |
SFC |
Support FIFO Configuration. |
SFD |
Support FIFO Data. |
SFFR |
SPI FIFO Fill Status Register. |
SFI |
Support FIFO Interrupt Mask. |
SFID1A |
Start Frame ID Byte 1 Path A. |
SFID1B |
Start Frame ID Byte 1 Path B. |
SFID2A |
Start Frame ID Byte 2 Path A. |
SFID2B |
Start Frame ID Byte 2 Path B. |
SFID3A |
Start Frame ID Byte 3 Path A. |
SFID3B |
Start Frame ID Byte 3 Path B. |
SFID4A |
Start Frame ID Byte 4 Path A. |
SFID4B |
Start Frame ID Byte 4 Path B. |
SFIDCA |
Start Frame ID Configuration Path A. |
SFIDCB |
Start Frame ID Configuration Path B. |
SFIDLA |
Start Frame ID Length Path A. |
SFIDLB |
Start Frame ID Length Path B. |
SFIR |
SPI FIFO Interrupt Register. |
SFL |
Support FIFO Fill Level. |
SFRP |
Support FIFO Read Pointer. |
SFS |
Support FIFO Status. |
SFWP |
Support FIFO Write Pointer. |
SMCR |
Sleep Mode Control Register. |
SOTC1A |
Start Of Telegram Conditions 1 Path A. |
SOTC1B |
Start Of Telegram Conditions 1 Path B. |
SOTC2A |
Start Of Telegram Conditions 2 Path A. |
SOTC2B |
Start Of Telegram Conditions 2 Path B. |
SOTCA |
Start Of Telegram Conditions Path A. |
SOTCB |
Start Of Telegram Conditions Path B. |
SOTSA |
Start Of Telegram Status Path A. |
SOTSB |
Start Of Telegram Status Path B. |
SOTTOA |
Start Of Telegram Time Out Path A. |
SOTTOB |
Start Of Telegram Time Out Path B. |
SP |
Stack Pointer. |
SPARE1 |
RF Front End Spare Register 1. |
SPCR |
SPI Control Register. |
SPDR |
SPI Data Register. |
SPH |
Stack Pointer high byte. |
SPL |
Stack Pointer low byte. |
SPMCSR |
Store Program Memory Control and Status Register. |
SPSR |
SPI Status Register. |
SRCCAL |
Slow RC Oscillator Calibration. |
SREG |
Status Register. |
SSMCR |
Sequencer State Machine Control Register. |
SSMFBR |
Sequencer State Machine Filter Bandwidth Register. |
SSMFCR |
Sequencer State Machine Flow Control Register. |
SSMIFR |
Sequencer State Machine Interrupt Flag Register. |
SSMIMR |
Sequencer State Machine Interrupt Mask Register. |
SSMRCR |
Sequencer State Machine Rx Control Register. |
SSMRR |
Sequencer State Machine Run Register. |
SSMSR |
Sequencer State Machine Status Register. |
SSMSTR |
Sequencer State Machine State Register. |
SSMXSR |
Sequencer State Machine Extended State Register. |
SUPCA1 |
Supply Calibration 1. |
SUPCA2 |
Supply Calibration 2. |
SUPCA3 |
Supply Calibration 3. |
SUPCA4 |
Supply Calibration 4. |
SUPCR |
Supply Control Register. |
SUPFR |
Supply Flag Register. |
SYCA |
Symbol Check Configuration Path A. |
SYCB |
Symbol Check Configuration Path B. |
T0CR |
Timer0 Control Register. |
T0IFR |
Timer0 Interrupt Flag Register. |
T1CNT |
Timer1 Counter Register. |
T1COR |
Timer1 Compare Register. |
T1CR |
Timer1 Control Register. |
T1IFR |
Timer1 Interrupt Flag Register. |
T1IMR |
Timer1 Interrupt Mask Register. |
T1MR |
Timer1 Mode Register. |
T2CNT |
Timer2 Counter Register. |
T2COR |
Timer2 Compare Register. |
T2CR |
Timer2 Control Register. |
T2IFR |
Timer2 Interrupt Flag Register. |
T2IMR |
Timer2 Interrupt Mask Register. |
T2MR |
Timer2 Mode Register. |
T3CNT |
Timer3 Counter. |
T3CNTH |
Timer3 Counter high byte. |
T3CNTL |
Timer3 Counter low byte. |
T3COR |
Timer3 Compare. |
T3CORH |
Timer3 Compare high byte. |
T3CORL |
Timer3 Compare low byte. |
T3CR |
Timer3 Control Register. |
T3ICR |
Timer3 Input Capture. |
T3ICRH |
Timer3 Input Capture high byte. |
T3ICRL |
Timer3 Input Capture low byte. |
T3IFR |
Timer3 Interrupt Flag Register. |
T3IMR |
Timer3 Interrupt Mask Register. |
T3MRA |
Timer3 Mode Register A. |
T3MRB |
Timer3 Mode Register B. |
T4CNT |
Timer4 Counter. |
T4CNTH |
Timer4 Counter high byte. |
T4CNTL |
Timer4 Counter low byte. |
T4COR |
Timer4 Compare. |
T4CORH |
Timer4 Compare high byte. |
T4CORL |
Timer4 Compare low byte. |
T4CR |
Timer4 Control Register. |
T4ICR |
Timer4 Input Capture. |
T4ICRH |
Timer4 Input Capture high byte. |
T4ICRL |
Timer4 Input Capture low byte. |
T4IFR |
Timer4 Interrupt Flag Register. |
T4IMR |
Timer4 Interrupt Mask Register. |
T4MRA |
Timer4 Mode Register A. |
T4MRB |
Timer4 Mode Register B. |
T5CCR |
Timer5 Configuration and Control Register. |
T5CNT |
Timer5 Counter. |
T5CNTH |
Timer5 Counter high byte. |
T5CNTL |
Timer5 Counter low byte. |
T5IFR |
Timer5 Interrupt Flag Register. |
T5IMR |
Timer5 Interrupt Mask Register. |
T5OCR |
Timer5 Output Compare. |
T5OCRH |
Timer5 Output Compare high byte. |
T5OCRL |
Timer5 Output Compare low byte. |
TEMP |
Temperature. |
TEMPH |
Temperature high byte. |
TEMPL |
Temperature low byte. |
TESRA |
Telegram Status Register Path A. |
TESRB |
Telegram Status Register Path B. |
TRCCR |
Trace Unit Control Register. |
TRCDR |
Trace Unit Data Register. |
TRCID |
Trace Identifier. |
TRCIDH |
Trace Identifier high byte. |
TRCIDL |
Trace Identifier low byte. |
VMCSR |
Voltage Monitor Control and Status Register. |
WCOTOA |
Wake Check Ok Time-Out Path A. |
WCOTOB |
Wake Check Ok Time-Out Path B. |
WDTCR |
Watchdog Timer0 Control Register. |
WUP1A |
Wake-Up Pattern Byte 1 Path A. |
WUP1B |
Wake-Up Pattern Byte 1 Path B. |
WUP2A |
Wake-Up Pattern Byte 2 Path A. |
WUP2B |
Wake-Up Pattern Byte 2 Path B. |
WUP3A |
Wake-Up Pattern Byte 3 Path A. |
WUP3B |
Wake-Up Pattern Byte 3 Path B. |
WUP4A |
Wake-Up Pattern Byte 4 Path A. |
WUP4B |
Wake-Up Pattern Byte 4 Path B. |
WUPLA |
Wake-Up Pattern Length Path A. |
WUPLB |
Wake-Up Pattern Length Path B. |
WUPTA |
Wake-Up Pattern Threshold Path A. |
WUPTB |
Wake-Up Pattern Threshold Path B. |
XFUSE |
XROW Fuse. |