Module avrd::ata5781

The AVR ATA5781 microcontroller

Variants

	Pinout	Package	Operating temperature	Operating voltage	Max speed
standard			0°C - 0°C	2.4V - 5.5V	0 MHz

Registers by module (not exhaustive)

EEPROM modules

• EEPROM

INT modules

• INT

Constants

CALRDY	Calibration ready signature.
CHCR	Channel Filter Configuration Register.
CHDN	Channel Filter Down Sampling Register.
CLKOCR	Clock output control Register.
CLKOD	Clock output divider settings Register.
CLPR	Clock Prescaler Register.
CMCR	Clock Management Control Register.
CMIMR	Clock Interrupt Mask Register.
CMOCR	Clock management override control register.
CMSR	Clock management status Register.
CRCCR	CRC Control Register.
CRCDIR	CRC Data Input Register.
CRCDOR	CRC Data Output Register.
DBCR	DeBounce Control Register.
DBENB	DeBounce Enable Port B.
DBENC	DeBounce Enable Port C.
DBGSW	Debugging Support Switch.
DBTC	Debounce Timer Compare Register.
DDRB	Port B Data Direction Register.
DDRC	Port C Data Direction Register.
DFC	Data FIFO Configuration Register.
DFD	Data FIFO Data Register.
DFI	Data FIFO Interrupt Mask Register.
DFL	Data FIFO Fill Level Register.
DFRP	Data FIFO Read Pointer.
DFS	Data FIFO Status Register.
DFTL	Data FIFO Telegram Length.
DFTLH	Data FIFO Telegram Length high byte.
DFTLL	Data FIFO Telegram Length low byte.
DFWP	Data FIFO Write Pointer.
DMCDA	Demodulator Carrier Detect for path A.
DMCDB	Demodulator Carrier Detect for path B.
DMCRA	Demodulator Control Register for path A.
DMCRB	Demodulator Control Register for path B.
DMDRA	Demodulator Data Rate on path A.
DMDRB	Demodulator Data Rate on path B.
DMMA	Demodulator Mode for path A.
DMMB	Demodulator Mode for Path B.
DWDR	debugWire communication Register.
EEAR	EEPROM Address Register.
EEARH	EEPROM Address Register high byte.
EEARL	EEPROM Address Register low byte.
EECR	EEPROM Control Register.
EECR2	EEPROM Control Register 2.
EEDR	EEPROM Data Register.
EEPR	EEPROM Protection Register.
EEST	EEPROM Status Register.
EICRA	External Interrupt control Register.
EIFR	External Interrupt Flag Register.
EIMSK	External Interrupt Mask Register.
EOTC1A	End Of Telegram Conditions 1 for Path A.
EOTC1B	End Of Telegram Conditions 1 for Path B.
EOTC2A	End Of Telegram Conditions 2 for Path A.
EOTC2B	End Of Telegram Conditions 2 for Path B.
EOTC3A	End Of Telegram Conditions 3 for Path A.
EOTC3B	End Of Telegram Conditions 3 for Path B.
EOTCA	End Of Telegram Conditions for path A.
EOTCB	End Of Telegram Conditions for path B.
EOTSA	End Of Telegram Status on path A.
EOTSB	End Of Telegram Status on path B.
FEALR	Front-End Antenna Level Detector Range.
FEANT	Front-End ANTenna.
FEBIA	Front-End IF Amplifier BIAS.
FEBT	Front-End RC Tuning Register.
FECR	Front-End Control Register.
FEEN1	Front-End Enable Register 1.
FEEN2	Front-End Enable Register 2.
FELNA	Front-End LNA Bias Register.
FEMS	Front-End Main and Swallow Control Register.
FESR	Front-End Status Register.
FETN4	Front-End RC Tuning 4bit Register.
FEVCO	Front-End VCO and PLL control.
FEVCT	Front-End VCO Tuning Register.
FFREQ1H	Fractional Frequency 1 Setting, High Byte.
FFREQ1L	Fractional Frequency 1 Setting, Low Byte.
FFREQ1M	Fractional Frequency 1 Setting, Middle Byte.
FFREQ2H	Fractional Frequency 2 Setting, High Byte.
FFREQ2L	Fractional Frequency 2 Setting, Low Byte.
FFREQ2M	Fractional Frequency 2 Setting, Middle Byte.
FRCCAL	Fast RC oscillator calibration Register.
FSEN	Frequency Synthesizer Enable register.
GPIOR0	General Purpose I/O Register 0.
GPIOR1	General Purpose I/O Register 1.
GPIOR2	General Purpose I/O Register 2.
GPIOR3	General Purpose I/O Register 3.
GPIOR4	General Purpose I/O Register 4.
GPIOR5	General Purpose I/O Register 5.
GPIOR6	General Purpose I/O Register 6.
GTCCR	General Timer/Counter Control Register.
GTCR	Get Telegram Control Register.
IDB0	ID Byte 0.
IDB1	ID Byte 1.
IDB2	ID Byte 2.
IDB3	ID Byte 3.
IDC	ID Configuration.
IDS	ID Status.
LOCKBIT
LOW
MCUCR	MCU Control Register.
MCUSR	MCU Status Register.
MSMCR1	Master State Machine Control Register 1.
MSMCR2	Master State Machine Control Register 2.
MSMCR3	Master State Machine Control Register 3.
MSMCR4	Master State Machine Control Register 4.
MSMSTR	Master State Machine state register.
PCICR	Pin change Interrupt control Register.
PCIFR	Pin change Interrupt flag Register.
PCMSK0	Pin change Mask Register 0.
PCMSK1	Pin change Mask Register 1.
PGMST	Program Memory Status Register.
PINB	Port B Input Pins.
PINC	Port C Input Pins.
PORTB	Port B Data Register.
PORTC	Port C Data Register.
PRR0	Power Reduction Register 0.
PRR1	Power Reduction Register 1.
PRR2	Power Reduction Register 2.
RDCR	Rx DSP control register.
RDOCR	Rx DSP output control.
RDPR	Rx DSP power reduction register.
RDSIFR	Rx DSP status interrupt flag register.
RDSIMR	Rx DSP status interrupt mask register.
RSCOM	RSSI Compensation Register.
RSHDV	RSSI High Band Damping Value.
RSIFG	RSSI High IF Amplifier Gain.
RSLDV	RSSI Low Band Damping Value.
RSSAV	RSSI Average Value.
RSSC	RSSI Configuration Register.
RSSH	RSSI High Threshold for Signal Check.
RSSL	RSSI Low Threshold for Signal Check.
RSSPK	RSSI Peak Value.
RXBC1	Rx Buffer configuration register 1.
RXBC2	Rx Buffer configuration register 2.
RXCIHA	Rx CRC Init value (16-bit RXCI) high byte for data path A.
RXCIHB	Rx CRC Init value (16-bit RXCI) high byte for data path B.
RXCILA	Rx CRC Init value (16-bit RXCI) low byte for data path A.
RXCILB	Rx CRC Init value (16-bit RXCI) low byte for data path B.
RXCPHA	Rx CRC polynomial (15 bit RXCPA) high byte for data path A.
RXCPHB	Rx CRC polynomial (15 bit RXCPB) high byte for data path B.
RXCPLA	Rx CRC polynomial low byte for data path A.
RXCPLB	Rx CRC polynomial low byte for data path B.
RXCRHA	Rx CRC result register high byte for data path A.
RXCRHB	Rx CRC result register high byte for data path B.
RXCRLA	Rx CRC result register low byte for data path A.
RXCRLB	Rx CRC result register low byte for data path B.
RXCSBA	Rx CRC skip bit number for data path A.
RXCSBB	Rx CRC skip bit number for data path B.
RXDSA	Rx data shift register for data path A.
RXDSB	Rx data shift register for data path B.
RXFOA	Received Frequency Offset vs Intermediate Frequency on path A.
RXFOB	Received Frequency Offset vs Intermediate Frequency on path B.
RXTLHA	Rx data telegram length register high byte for data path A.
RXTLHB	Rx data telegram length register high byte for data path B.
RXTLLA	Rx data telegram length register low byte for data path A.
RXTLLB	Rx data telegram length register low byte for data path B.
SFC	Support FIFO Configuration Register.
SFD	Support FIFO Data Register.
SFFR	SPI FIFO Fill Status Register.
SFI	Support FIFO Interrupt Mask Register.
SFID1A	Start-Frame ID byte 1 for data path A.
SFID1B	Start-Frame ID byte 1 for data path B.
SFID2A	Start-Frame ID byte 2 for data path A.
SFID2B	Start-Frame ID byte 2 for data path B.
SFID3A	Start-Frame ID byte 3 for data path A.
SFID3B	Start-Frame ID byte 3 for data path B.
SFID4A	Start-Frame ID byte 4 for data path A.
SFID4B	Start-Frame ID byte 4 for data path B.
SFIDCA	Start-Frame ID Control for data path A.
SFIDCB	Start-Frame ID Control for data path B.
SFIDLA	Start-Frame ID Length for data path A.
SFIDLB	Start-Frame ID Length for data path B.
SFIR	SPI FIFO Interrupt Register.
SFL	Support FIFO Fill Level Register.
SFRP	Support FIFO Read Pointer.
SFS	Support FIFO Status Register.
SFWP	Support FIFO Write Pointer.
SMCR	Sleep mode control Register.
SOTC1A	Start Of Telegram Conditions 1 for Path A.
SOTC1B	Start Of Telegram Conditions 1 for Path B.
SOTC2A	Start Of Telegram Conditions 2 for Path A.
SOTC2B	Start Of Telegram Conditions 2 for Path B.
SOTCA	Start Of Telegram Conditions for path A.
SOTCB	Start Of Telegram Conditions for path B.
SOTSA	Start Of Telegram Status for path A.
SOTSB	Start Of Telegram Status for path B.
SOTTOA	Start Of Telegram Time Out for path A.
SOTTOB	Start Of Telegram Time Out for path B.
SP	Stack Pointer.
SPCR	SPI Control Register.
SPDR	SPI Data Register.
SPH	Stack Pointer high byte.
SPL	Stack Pointer low byte.
SPMCSR	Store Program Memory Control and Status Register.
SPSR	SPI Status Register.
SRCCAL	Slow RC oscillator calibration Register.
SREG	Status Register.
SSMCR	SSM Control Register.
SSMFBR	SSM Filter Bandwidth Register.
SSMFCR	SSM Flow Control Register.
SSMIFR	SSM Interrupt Flag Register.
SSMIMR	SSM interrupt mask register.
SSMRCR	SSM Rx Control Register.
SSMRR	SSM Run Register.
SSMSR	SSM Status Register.
SSMSTR	SSM State Register.
SSMXSR	SSM extended State Register.
SUPCA2	Supply calibration register 2.
SUPCA3	Supply calibration register 3.
SUPCA4	Supply calibration register 4.
SUPCR	Supply Control Register.
SUPFR	Supply Interrupt Flag Register.
SYCA	Symbol check configuration for data path A.
SYCB	Symbol check configuration for data path B.
T0CR	Timer0 Control Register.
T0IFR	Timer0 Interrupt Flag Register.
T1CNT	Timer1 Counter Register.
T1COR	Timer1 Compare Register.
T1CR	Timer1 control Register.
T1IFR	Timer1 Interrupt Flag Register.
T1IMR	Timer1 Interrupt Mask Register.
T1MR	Timer1 Mode Register.
T2CNT	Timer2 Counter Register.
T2COR	Timer2 Compare Register.
T2CR	Timer2 Control Register.
T2IFR	Timer2 Interrupt Flag Register.
T2IMR	Timer2 Interrupt Mask Register.
T2MR	Timer2 Mode Register.
T3CNT	Timer3 counter Register.
T3CNTH	Timer3 counter Register high byte.
T3CNTL	Timer3 counter Register low byte.
T3COR	Timer3 compare Register.
T3CORH	Timer3 compare Register high byte.
T3CORL	Timer3 compare Register low byte.
T3CR	Timer3 control Register.
T3ICR	Timer3 input capture Register.
T3ICRH	Timer3 input capture Register high byte.
T3ICRL	Timer3 input capture Register low byte.
T3IFR	Timer3 interrupt flag Register.
T3IMR	Timer3 interrupt mask Register.
T3MRA	Timer3 mode Register.
T3MRB	Timer3 mode Register.
T4CNT	Timer4 counter Register.
T4CNTH	Timer4 counter Register high byte.
T4CNTL	Timer4 counter Register low byte.
T4COR	Timer4 compare Register.
T4CORH	Timer4 compare Register high byte.
T4CORL	Timer4 compare Register low byte.
T4CR	Timer4 control Register.
T4ICR	Timer4 input capture Register.
T4ICRH	Timer4 input capture Register high byte.
T4ICRL	Timer4 input capture Register low byte.
T4IFR	Timer4 interrupt flag Register.
T4IMR	Timer4 interrupt mask Register.
T4MRA	Timer4 mode Register.
T4MRB	Timer4 mode Register.
T5CCR	Timer5 Control Register.
T5CNT	Timer5 Counter.
T5CNTH	Timer5 Counter high byte.
T5CNTL	Timer5 Counter low byte.
T5IFR	Timer5 Interrupt Flag Register.
T5IMR	Timer5 Interrupt Mask Register.
T5OCR	Timer5 Output Compare Register.
T5OCRH	Timer5 Output Compare Register high byte.
T5OCRL	Timer5 Output Compare Register low byte.
TEMPH	Temperature High byte.
TEMPL	Temperature Low byte.
TESRA	Telegram Status Register on Path A.
TESRB	Telegram Status Register on Path B.
VMCAL	Voltage Monitor Calibration register.
VMCSR	Voltage Monitor Control and Status Register.
WCOTOA	Wait check ok time out for path A.
WCOTOB	Wait check ok time out for path B.
WDTCR	Watchdog Timer0 control Register.
WUP1A	Wake-Up Pattern byte 1 for data path A.
WUP1B	Wake-Up Pattern byte 1 for data path B.
WUP2A	Wake-Up Pattern byte 2 for data path A.
WUP2B	Wake-Up Pattern byte 2 for data path B.
WUP3A	Wake-Up Pattern byte 3 for data path A.
WUP3B	Wake-Up Pattern byte 3 for data path B.
WUP4A	Wake-Up Pattern byte 4 for data path A.
WUP4B	Wake-Up Pattern byte 4 for data path B.
WUPLA	Wake-Up Pattern Length for data path A.
WUPLB	Wake-Up Pattern Length for data path B.
WUPTA	Wake-Up Pattern Threshold for data path A.
WUPTB	Wake-Up Pattern Threshold for data path B.
XFUSE