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#[doc = "Reader of register USICR"] pub type R = crate::R<u8, super::USICR>; #[doc = "Writer for register USICR"] pub type W = crate::W<u8, super::USICR>; #[doc = "Register USICR `reset()`'s with value 0"] impl crate::ResetValue for super::USICR { #[inline(always)] fn reset_value() -> Self::Ux { 0 } } #[doc = "Write proxy for field `USITC`"] pub struct USITC_W<'a> { w: &'a mut W, } impl<'a> USITC_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | ((value as u8) & 0x01); self.w } } #[doc = "Write proxy for field `USICLK`"] pub struct USICLK_W<'a> { w: &'a mut W, } impl<'a> USICLK_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u8) & 0x01) << 1); self.w } } #[doc = "USI Clock Source Select Bits\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] #[repr(u8)] pub enum USICS_A { #[doc = "0: No Clock/Software clock strobe"] NO_CLOCK = 0, #[doc = "1: Timer/Counter0 Compare Match"] TC0 = 1, #[doc = "2: External, positive edge"] EXT_POS = 2, #[doc = "3: External, negative edge"] EXT_NEG = 3, } impl From<USICS_A> for u8 { #[inline(always)] fn from(variant: USICS_A) -> Self { variant as _ } } #[doc = "Reader of field `USICS`"] pub type USICS_R = crate::R<u8, USICS_A>; impl USICS_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> USICS_A { match self.bits { 0 => USICS_A::NO_CLOCK, 1 => USICS_A::TC0, 2 => USICS_A::EXT_POS, 3 => USICS_A::EXT_NEG, _ => unreachable!(), } } #[doc = "Checks if the value of the field is `NO_CLOCK`"] #[inline(always)] pub fn is_no_clock(&self) -> bool { *self == USICS_A::NO_CLOCK } #[doc = "Checks if the value of the field is `TC0`"] #[inline(always)] pub fn is_tc0(&self) -> bool { *self == USICS_A::TC0 } #[doc = "Checks if the value of the field is `EXT_POS`"] #[inline(always)] pub fn is_ext_pos(&self) -> bool { *self == USICS_A::EXT_POS } #[doc = "Checks if the value of the field is `EXT_NEG`"] #[inline(always)] pub fn is_ext_neg(&self) -> bool { *self == USICS_A::EXT_NEG } } #[doc = "Write proxy for field `USICS`"] pub struct USICS_W<'a> { w: &'a mut W, } impl<'a> USICS_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: USICS_A) -> &'a mut W { self.bits(variant.into()) } #[doc = "No Clock/Software clock strobe"] #[inline(always)] pub fn no_clock(self) -> &'a mut W { self.variant(USICS_A::NO_CLOCK) } #[doc = "Timer/Counter0 Compare Match"] #[inline(always)] pub fn tc0(self) -> &'a mut W { self.variant(USICS_A::TC0) } #[doc = "External, positive edge"] #[inline(always)] pub fn ext_pos(self) -> &'a mut W { self.variant(USICS_A::EXT_POS) } #[doc = "External, negative edge"] #[inline(always)] pub fn ext_neg(self) -> &'a mut W { self.variant(USICS_A::EXT_NEG) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u8) & 0x03) << 2); self.w } } #[doc = "USI Wire Mode Bits\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] #[repr(u8)] pub enum USIWM_A { #[doc = "0: All detectors disabled. Port pins operates as normal."] DISABLED = 0, #[doc = "1: Three-wire mode. Uses DO, DI, and USCK pins."] THREE_WIRE = 1, #[doc = "2: Two-wire mode (Slave). Uses SDA (DI) and SCL (USCK) pins."] TWO_WIRE_SLAVE = 2, #[doc = "3: Two-wire mode (Master). Uses SDA and SCL pins."] TWO_WIRE_MASTER = 3, } impl From<USIWM_A> for u8 { #[inline(always)] fn from(variant: USIWM_A) -> Self { variant as _ } } #[doc = "Reader of field `USIWM`"] pub type USIWM_R = crate::R<u8, USIWM_A>; impl USIWM_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> USIWM_A { match self.bits { 0 => USIWM_A::DISABLED, 1 => USIWM_A::THREE_WIRE, 2 => USIWM_A::TWO_WIRE_SLAVE, 3 => USIWM_A::TWO_WIRE_MASTER, _ => unreachable!(), } } #[doc = "Checks if the value of the field is `DISABLED`"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == USIWM_A::DISABLED } #[doc = "Checks if the value of the field is `THREE_WIRE`"] #[inline(always)] pub fn is_three_wire(&self) -> bool { *self == USIWM_A::THREE_WIRE } #[doc = "Checks if the value of the field is `TWO_WIRE_SLAVE`"] #[inline(always)] pub fn is_two_wire_slave(&self) -> bool { *self == USIWM_A::TWO_WIRE_SLAVE } #[doc = "Checks if the value of the field is `TWO_WIRE_MASTER`"] #[inline(always)] pub fn is_two_wire_master(&self) -> bool { *self == USIWM_A::TWO_WIRE_MASTER } } #[doc = "Write proxy for field `USIWM`"] pub struct USIWM_W<'a> { w: &'a mut W, } impl<'a> USIWM_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: USIWM_A) -> &'a mut W { self.bits(variant.into()) } #[doc = "All detectors disabled. Port pins operates as normal."] #[inline(always)] pub fn disabled(self) -> &'a mut W { self.variant(USIWM_A::DISABLED) } #[doc = "Three-wire mode. Uses DO, DI, and USCK pins."] #[inline(always)] pub fn three_wire(self) -> &'a mut W { self.variant(USIWM_A::THREE_WIRE) } #[doc = "Two-wire mode (Slave). Uses SDA (DI) and SCL (USCK) pins."] #[inline(always)] pub fn two_wire_slave(self) -> &'a mut W { self.variant(USIWM_A::TWO_WIRE_SLAVE) } #[doc = "Two-wire mode (Master). Uses SDA and SCL pins."] #[inline(always)] pub fn two_wire_master(self) -> &'a mut W { self.variant(USIWM_A::TWO_WIRE_MASTER) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u8) & 0x03) << 4); self.w } } #[doc = "Reader of field `USIOIE`"] pub type USIOIE_R = crate::R<bool, bool>; #[doc = "Write proxy for field `USIOIE`"] pub struct USIOIE_W<'a> { w: &'a mut W, } impl<'a> USIOIE_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u8) & 0x01) << 6); self.w } } #[doc = "Reader of field `USISIE`"] pub type USISIE_R = crate::R<bool, bool>; #[doc = "Write proxy for field `USISIE`"] pub struct USISIE_W<'a> { w: &'a mut W, } impl<'a> USISIE_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u8) & 0x01) << 7); self.w } } impl R { #[doc = "Bits 2:3 - USI Clock Source Select Bits"] #[inline(always)] pub fn usics(&self) -> USICS_R { USICS_R::new(((self.bits >> 2) & 0x03) as u8) } #[doc = "Bits 4:5 - USI Wire Mode Bits"] #[inline(always)] pub fn usiwm(&self) -> USIWM_R { USIWM_R::new(((self.bits >> 4) & 0x03) as u8) } #[doc = "Bit 6 - Counter Overflow Interrupt Enable"] #[inline(always)] pub fn usioie(&self) -> USIOIE_R { USIOIE_R::new(((self.bits >> 6) & 0x01) != 0) } #[doc = "Bit 7 - Start Condition Interrupt Enable"] #[inline(always)] pub fn usisie(&self) -> USISIE_R { USISIE_R::new(((self.bits >> 7) & 0x01) != 0) } } impl W { #[doc = "Bit 0 - Toggle Clock Port Pin"] #[inline(always)] pub fn usitc(&mut self) -> USITC_W { USITC_W { w: self } } #[doc = "Bit 1 - Clock Strobe"] #[inline(always)] pub fn usiclk(&mut self) -> USICLK_W { USICLK_W { w: self } } #[doc = "Bits 2:3 - USI Clock Source Select Bits"] #[inline(always)] pub fn usics(&mut self) -> USICS_W { USICS_W { w: self } } #[doc = "Bits 4:5 - USI Wire Mode Bits"] #[inline(always)] pub fn usiwm(&mut self) -> USIWM_W { USIWM_W { w: self } } #[doc = "Bit 6 - Counter Overflow Interrupt Enable"] #[inline(always)] pub fn usioie(&mut self) -> USIOIE_W { USIOIE_W { w: self } } #[doc = "Bit 7 - Start Condition Interrupt Enable"] #[inline(always)] pub fn usisie(&mut self) -> USISIE_W { USISIE_W { w: self } } }