#[doc = "Reader of register LOW"]
pub type R = crate::R<u8, super::LOW>;
#[doc = "Writer for register LOW"]
pub type W = crate::W<u8, super::LOW>;
#[doc = "Register LOW `reset()`'s with value 0"]
impl crate::ResetValue for super::LOW {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}
#[doc = "Select Clock source\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum SUT_CKSEL_A {
#[doc = "0: Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms"]
EXTCLK_6CK_14CK_0MS = 0,
#[doc = "1: PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms"]
PLLCLK_1KCK_14CK_4MS = 1,
#[doc = "2: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms"]
INTRCOSC_8MHZ_6CK_14CK_0MS = 2,
#[doc = "3: ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms"]
INTRCOSC_6MHZ4_6CK_14CK_64MS = 3,
#[doc = "4: WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms"]
WDOSC_128KHZ_6CK_14CK_0MS = 4,
#[doc = "6: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms"]
EXTLOFXTAL_1KCK_14CK_0MS = 6,
#[doc = "8: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"]
EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1 = 8,
#[doc = "9: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms"]
EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS = 9,
#[doc = "10: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"]
EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1 = 10,
#[doc = "11: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms"]
EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS = 11,
#[doc = "12: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"]
EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1 = 12,
#[doc = "13: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms"]
EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS = 13,
#[doc = "14: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"]
EXTXOSC_8MHZ_XX_258CK_14CK_4MS1 = 14,
#[doc = "15: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms"]
EXTXOSC_8MHZ_XX_1KCK_14CK_65MS = 15,
#[doc = "16: Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"]
EXTCLK_6CK_14CK_4MS1 = 16,
#[doc = "17: PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4 ms"]
PLLCLK_16KCK_14CK_4MS = 17,
#[doc = "18: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms"]
INTRCOSC_8MHZ_6CK_14CK_4MS = 18,
#[doc = "20: WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms"]
WDOSC_128KHZ_6CK_14CK_4MS = 20,
#[doc = "22: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms"]
EXTLOFXTAL_1KCK_14CK_4MS = 22,
#[doc = "24: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms"]
EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS = 24,
#[doc = "25: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"]
EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS = 25,
#[doc = "26: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms"]
EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS = 26,
#[doc = "27: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"]
EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS = 27,
#[doc = "28: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms"]
EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS = 28,
#[doc = "29: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"]
EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS = 29,
#[doc = "30: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms"]
EXTXOSC_8MHZ_XX_258CK_14CK_65MS = 30,
#[doc = "31: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"]
EXTXOSC_8MHZ_XX_16KCK_14CK_0MS = 31,
#[doc = "32: Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms"]
EXTCLK_6CK_14CK_65MS = 32,
#[doc = "33: PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 64 ms"]
PLLCLK_1KCK_14CK_64MS = 33,
#[doc = "34: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms"]
INTRCOSC_8MHZ_6CK_14CK_64MS = 34,
#[doc = "35: ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms"]
INTRCOSC_6MHZ4_6CK_14CK_4MS = 35,
#[doc = "36: WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms"]
WDOSC_128KHZ_6CK_14CK_64MS = 36,
#[doc = "38: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 64 ms"]
EXTLOFXTAL_32KCK_14CK_64MS = 38,
#[doc = "40: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms"]
EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS = 40,
#[doc = "41: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms"]
EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 = 41,
#[doc = "42: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms"]
EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS = 42,
#[doc = "43: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms"]
EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 = 43,
#[doc = "44: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms"]
EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS = 44,
#[doc = "45: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms"]
EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 = 45,
#[doc = "46: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms"]
EXTXOSC_8MHZ_XX_1KCK_14CK_0MS = 46,
#[doc = "47: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms"]
EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 = 47,
#[doc = "49: PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 64 ms"]
PLLCLK_16KCK_14CK_64MS = 49,
#[doc = "51: ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 1 CK/14 CK + 0 ms"]
INTRCOSC_6MHZ4_1CK_14CK_0MS = 51,
#[doc = "56: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms"]
EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1 = 56,
#[doc = "57: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms"]
EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS = 57,
#[doc = "58: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms"]
EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1 = 58,
#[doc = "59: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms"]
EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS = 59,
#[doc = "60: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms"]
EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1 = 60,
#[doc = "61: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms"]
EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS = 61,
#[doc = "62: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms"]
EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1 = 62,
#[doc = "63: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms"]
EXTXOSC_8MHZ_XX_16KCK_14CK_65MS = 63,
}
impl From<SUT_CKSEL_A> for u8 {
#[inline(always)]
fn from(variant: SUT_CKSEL_A) -> Self {
variant as _
}
}
#[doc = "Reader of field `SUT_CKSEL`"]
pub type SUT_CKSEL_R = crate::R<u8, SUT_CKSEL_A>;
impl SUT_CKSEL_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> crate::Variant<u8, SUT_CKSEL_A> {
use crate::Variant::*;
match self.bits {
0 => Val(SUT_CKSEL_A::EXTCLK_6CK_14CK_0MS),
1 => Val(SUT_CKSEL_A::PLLCLK_1KCK_14CK_4MS),
2 => Val(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_0MS),
3 => Val(SUT_CKSEL_A::INTRCOSC_6MHZ4_6CK_14CK_64MS),
4 => Val(SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_0MS),
6 => Val(SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_0MS),
8 => Val(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1),
9 => Val(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS),
10 => Val(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1),
11 => Val(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS),
12 => Val(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1),
13 => Val(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS),
14 => Val(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_4MS1),
15 => Val(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_65MS),
16 => Val(SUT_CKSEL_A::EXTCLK_6CK_14CK_4MS1),
17 => Val(SUT_CKSEL_A::PLLCLK_16KCK_14CK_4MS),
18 => Val(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_4MS),
20 => Val(SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_4MS),
22 => Val(SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_4MS),
24 => Val(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS),
25 => Val(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS),
26 => Val(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS),
27 => Val(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS),
28 => Val(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS),
29 => Val(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS),
30 => Val(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_65MS),
31 => Val(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_0MS),
32 => Val(SUT_CKSEL_A::EXTCLK_6CK_14CK_65MS),
33 => Val(SUT_CKSEL_A::PLLCLK_1KCK_14CK_64MS),
34 => Val(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_64MS),
35 => Val(SUT_CKSEL_A::INTRCOSC_6MHZ4_6CK_14CK_4MS),
36 => Val(SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_64MS),
38 => Val(SUT_CKSEL_A::EXTLOFXTAL_32KCK_14CK_64MS),
40 => Val(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS),
41 => Val(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1),
42 => Val(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS),
43 => Val(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1),
44 => Val(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS),
45 => Val(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1),
46 => Val(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_0MS),
47 => Val(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1),
49 => Val(SUT_CKSEL_A::PLLCLK_16KCK_14CK_64MS),
51 => Val(SUT_CKSEL_A::INTRCOSC_6MHZ4_1CK_14CK_0MS),
56 => Val(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1),
57 => Val(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS),
58 => Val(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1),
59 => Val(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS),
60 => Val(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1),
61 => Val(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS),
62 => Val(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1),
63 => Val(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_65MS),
i => Res(i),
}
}
#[doc = "Checks if the value of the field is `EXTCLK_6CK_14CK_0MS`"]
#[inline(always)]
pub fn is_extclk_6ck_14ck_0ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTCLK_6CK_14CK_0MS
}
#[doc = "Checks if the value of the field is `PLLCLK_1KCK_14CK_4MS`"]
#[inline(always)]
pub fn is_pllclk_1kck_14ck_4ms(&self) -> bool {
*self == SUT_CKSEL_A::PLLCLK_1KCK_14CK_4MS
}
#[doc = "Checks if the value of the field is `INTRCOSC_8MHZ_6CK_14CK_0MS`"]
#[inline(always)]
pub fn is_intrcosc_8mhz_6ck_14ck_0ms(&self) -> bool {
*self == SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_0MS
}
#[doc = "Checks if the value of the field is `INTRCOSC_6MHZ4_6CK_14CK_64MS`"]
#[inline(always)]
pub fn is_intrcosc_6mhz4_6ck_14ck_64ms(&self) -> bool {
*self == SUT_CKSEL_A::INTRCOSC_6MHZ4_6CK_14CK_64MS
}
#[doc = "Checks if the value of the field is `WDOSC_128KHZ_6CK_14CK_0MS`"]
#[inline(always)]
pub fn is_wdosc_128khz_6ck_14ck_0ms(&self) -> bool {
*self == SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_0MS
}
#[doc = "Checks if the value of the field is `EXTLOFXTAL_1KCK_14CK_0MS`"]
#[inline(always)]
pub fn is_extlofxtal_1kck_14ck_0ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_0MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1`"]
#[inline(always)]
pub fn is_extxosc_0mhz4_0mhz9_258ck_14ck_4ms1(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1
}
#[doc = "Checks if the value of the field is `EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS`"]
#[inline(always)]
pub fn is_extxosc_0mhz4_0mhz9_1kck_14ck_65ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1`"]
#[inline(always)]
pub fn is_extxosc_0mhz9_3mhz_258ck_14ck_4ms1(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1
}
#[doc = "Checks if the value of the field is `EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS`"]
#[inline(always)]
pub fn is_extxosc_0mhz9_3mhz_1kck_14ck_65ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1`"]
#[inline(always)]
pub fn is_extxosc_3mhz_8mhz_258ck_14ck_4ms1(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1
}
#[doc = "Checks if the value of the field is `EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS`"]
#[inline(always)]
pub fn is_extxosc_3mhz_8mhz_1kck_14ck_65ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_8MHZ_XX_258CK_14CK_4MS1`"]
#[inline(always)]
pub fn is_extxosc_8mhz_xx_258ck_14ck_4ms1(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_4MS1
}
#[doc = "Checks if the value of the field is `EXTXOSC_8MHZ_XX_1KCK_14CK_65MS`"]
#[inline(always)]
pub fn is_extxosc_8mhz_xx_1kck_14ck_65ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_65MS
}
#[doc = "Checks if the value of the field is `EXTCLK_6CK_14CK_4MS1`"]
#[inline(always)]
pub fn is_extclk_6ck_14ck_4ms1(&self) -> bool {
*self == SUT_CKSEL_A::EXTCLK_6CK_14CK_4MS1
}
#[doc = "Checks if the value of the field is `PLLCLK_16KCK_14CK_4MS`"]
#[inline(always)]
pub fn is_pllclk_16kck_14ck_4ms(&self) -> bool {
*self == SUT_CKSEL_A::PLLCLK_16KCK_14CK_4MS
}
#[doc = "Checks if the value of the field is `INTRCOSC_8MHZ_6CK_14CK_4MS`"]
#[inline(always)]
pub fn is_intrcosc_8mhz_6ck_14ck_4ms(&self) -> bool {
*self == SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_4MS
}
#[doc = "Checks if the value of the field is `WDOSC_128KHZ_6CK_14CK_4MS`"]
#[inline(always)]
pub fn is_wdosc_128khz_6ck_14ck_4ms(&self) -> bool {
*self == SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_4MS
}
#[doc = "Checks if the value of the field is `EXTLOFXTAL_1KCK_14CK_4MS`"]
#[inline(always)]
pub fn is_extlofxtal_1kck_14ck_4ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_4MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS`"]
#[inline(always)]
pub fn is_extxosc_0mhz4_0mhz9_258ck_14ck_65ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS`"]
#[inline(always)]
pub fn is_extxosc_0mhz4_0mhz9_16kck_14ck_0ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS`"]
#[inline(always)]
pub fn is_extxosc_0mhz9_3mhz_258ck_14ck_65ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS`"]
#[inline(always)]
pub fn is_extxosc_0mhz9_3mhz_16kck_14ck_0ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS`"]
#[inline(always)]
pub fn is_extxosc_3mhz_8mhz_258ck_14ck_65ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS`"]
#[inline(always)]
pub fn is_extxosc_3mhz_8mhz_16kck_14ck_0ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_8MHZ_XX_258CK_14CK_65MS`"]
#[inline(always)]
pub fn is_extxosc_8mhz_xx_258ck_14ck_65ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_65MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_8MHZ_XX_16KCK_14CK_0MS`"]
#[inline(always)]
pub fn is_extxosc_8mhz_xx_16kck_14ck_0ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_0MS
}
#[doc = "Checks if the value of the field is `EXTCLK_6CK_14CK_65MS`"]
#[inline(always)]
pub fn is_extclk_6ck_14ck_65ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTCLK_6CK_14CK_65MS
}
#[doc = "Checks if the value of the field is `PLLCLK_1KCK_14CK_64MS`"]
#[inline(always)]
pub fn is_pllclk_1kck_14ck_64ms(&self) -> bool {
*self == SUT_CKSEL_A::PLLCLK_1KCK_14CK_64MS
}
#[doc = "Checks if the value of the field is `INTRCOSC_8MHZ_6CK_14CK_64MS`"]
#[inline(always)]
pub fn is_intrcosc_8mhz_6ck_14ck_64ms(&self) -> bool {
*self == SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_64MS
}
#[doc = "Checks if the value of the field is `INTRCOSC_6MHZ4_6CK_14CK_4MS`"]
#[inline(always)]
pub fn is_intrcosc_6mhz4_6ck_14ck_4ms(&self) -> bool {
*self == SUT_CKSEL_A::INTRCOSC_6MHZ4_6CK_14CK_4MS
}
#[doc = "Checks if the value of the field is `WDOSC_128KHZ_6CK_14CK_64MS`"]
#[inline(always)]
pub fn is_wdosc_128khz_6ck_14ck_64ms(&self) -> bool {
*self == SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_64MS
}
#[doc = "Checks if the value of the field is `EXTLOFXTAL_32KCK_14CK_64MS`"]
#[inline(always)]
pub fn is_extlofxtal_32kck_14ck_64ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTLOFXTAL_32KCK_14CK_64MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS`"]
#[inline(always)]
pub fn is_extxosc_0mhz4_0mhz9_1kck_14ck_0ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1`"]
#[inline(always)]
pub fn is_extxosc_0mhz4_0mhz9_16kck_14ck_4ms1(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1
}
#[doc = "Checks if the value of the field is `EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS`"]
#[inline(always)]
pub fn is_extxosc_0mhz9_3mhz_1kck_14ck_0ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1`"]
#[inline(always)]
pub fn is_extxosc_0mhz9_3mhz_16kck_14ck_4ms1(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1
}
#[doc = "Checks if the value of the field is `EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS`"]
#[inline(always)]
pub fn is_extxosc_3mhz_8mhz_1kck_14ck_0ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1`"]
#[inline(always)]
pub fn is_extxosc_3mhz_8mhz_16kck_14ck_4ms1(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1
}
#[doc = "Checks if the value of the field is `EXTXOSC_8MHZ_XX_1KCK_14CK_0MS`"]
#[inline(always)]
pub fn is_extxosc_8mhz_xx_1kck_14ck_0ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_0MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1`"]
#[inline(always)]
pub fn is_extxosc_8mhz_xx_16kck_14ck_4ms1(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1
}
#[doc = "Checks if the value of the field is `PLLCLK_16KCK_14CK_64MS`"]
#[inline(always)]
pub fn is_pllclk_16kck_14ck_64ms(&self) -> bool {
*self == SUT_CKSEL_A::PLLCLK_16KCK_14CK_64MS
}
#[doc = "Checks if the value of the field is `INTRCOSC_6MHZ4_1CK_14CK_0MS`"]
#[inline(always)]
pub fn is_intrcosc_6mhz4_1ck_14ck_0ms(&self) -> bool {
*self == SUT_CKSEL_A::INTRCOSC_6MHZ4_1CK_14CK_0MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1`"]
#[inline(always)]
pub fn is_extxosc_0mhz4_0mhz9_1kck_14ck_4ms1(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1
}
#[doc = "Checks if the value of the field is `EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS`"]
#[inline(always)]
pub fn is_extxosc_0mhz4_0mhz9_16kck_14ck_65ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1`"]
#[inline(always)]
pub fn is_extxosc_0mhz9_3mhz_1kck_14ck_4ms1(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1
}
#[doc = "Checks if the value of the field is `EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS`"]
#[inline(always)]
pub fn is_extxosc_0mhz9_3mhz_16kck_14ck_65ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1`"]
#[inline(always)]
pub fn is_extxosc_3mhz_8mhz_1kck_14ck_4ms1(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1
}
#[doc = "Checks if the value of the field is `EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS`"]
#[inline(always)]
pub fn is_extxosc_3mhz_8mhz_16kck_14ck_65ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS
}
#[doc = "Checks if the value of the field is `EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1`"]
#[inline(always)]
pub fn is_extxosc_8mhz_xx_1kck_14ck_4ms1(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1
}
#[doc = "Checks if the value of the field is `EXTXOSC_8MHZ_XX_16KCK_14CK_65MS`"]
#[inline(always)]
pub fn is_extxosc_8mhz_xx_16kck_14ck_65ms(&self) -> bool {
*self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_65MS
}
}
#[doc = "Write proxy for field `SUT_CKSEL`"]
pub struct SUT_CKSEL_W<'a> {
w: &'a mut W,
}
impl<'a> SUT_CKSEL_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SUT_CKSEL_A) -> &'a mut W {
unsafe { self.bits(variant.into()) }
}
#[doc = "Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms"]
#[inline(always)]
pub fn extclk_6ck_14ck_0ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTCLK_6CK_14CK_0MS)
}
#[doc = "PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms"]
#[inline(always)]
pub fn pllclk_1kck_14ck_4ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::PLLCLK_1KCK_14CK_4MS)
}
#[doc = "Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms"]
#[inline(always)]
pub fn intrcosc_8mhz_6ck_14ck_0ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_0MS)
}
#[doc = "ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms"]
#[inline(always)]
pub fn intrcosc_6mhz4_6ck_14ck_64ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::INTRCOSC_6MHZ4_6CK_14CK_64MS)
}
#[doc = "WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms"]
#[inline(always)]
pub fn wdosc_128khz_6ck_14ck_0ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_0MS)
}
#[doc = "Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms"]
#[inline(always)]
pub fn extlofxtal_1kck_14ck_0ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_0MS)
}
#[doc = "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"]
#[inline(always)]
pub fn extxosc_0mhz4_0mhz9_258ck_14ck_4ms1(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1)
}
#[doc = "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms"]
#[inline(always)]
pub fn extxosc_0mhz4_0mhz9_1kck_14ck_65ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS)
}
#[doc = "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"]
#[inline(always)]
pub fn extxosc_0mhz9_3mhz_258ck_14ck_4ms1(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1)
}
#[doc = "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms"]
#[inline(always)]
pub fn extxosc_0mhz9_3mhz_1kck_14ck_65ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS)
}
#[doc = "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"]
#[inline(always)]
pub fn extxosc_3mhz_8mhz_258ck_14ck_4ms1(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1)
}
#[doc = "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms"]
#[inline(always)]
pub fn extxosc_3mhz_8mhz_1kck_14ck_65ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS)
}
#[doc = "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"]
#[inline(always)]
pub fn extxosc_8mhz_xx_258ck_14ck_4ms1(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_4MS1)
}
#[doc = "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms"]
#[inline(always)]
pub fn extxosc_8mhz_xx_1kck_14ck_65ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_65MS)
}
#[doc = "Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"]
#[inline(always)]
pub fn extclk_6ck_14ck_4ms1(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTCLK_6CK_14CK_4MS1)
}
#[doc = "PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4 ms"]
#[inline(always)]
pub fn pllclk_16kck_14ck_4ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::PLLCLK_16KCK_14CK_4MS)
}
#[doc = "Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms"]
#[inline(always)]
pub fn intrcosc_8mhz_6ck_14ck_4ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_4MS)
}
#[doc = "WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms"]
#[inline(always)]
pub fn wdosc_128khz_6ck_14ck_4ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_4MS)
}
#[doc = "Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms"]
#[inline(always)]
pub fn extlofxtal_1kck_14ck_4ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_4MS)
}
#[doc = "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms"]
#[inline(always)]
pub fn extxosc_0mhz4_0mhz9_258ck_14ck_65ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS)
}
#[doc = "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"]
#[inline(always)]
pub fn extxosc_0mhz4_0mhz9_16kck_14ck_0ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS)
}
#[doc = "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms"]
#[inline(always)]
pub fn extxosc_0mhz9_3mhz_258ck_14ck_65ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS)
}
#[doc = "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"]
#[inline(always)]
pub fn extxosc_0mhz9_3mhz_16kck_14ck_0ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS)
}
#[doc = "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms"]
#[inline(always)]
pub fn extxosc_3mhz_8mhz_258ck_14ck_65ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS)
}
#[doc = "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"]
#[inline(always)]
pub fn extxosc_3mhz_8mhz_16kck_14ck_0ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS)
}
#[doc = "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms"]
#[inline(always)]
pub fn extxosc_8mhz_xx_258ck_14ck_65ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_65MS)
}
#[doc = "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"]
#[inline(always)]
pub fn extxosc_8mhz_xx_16kck_14ck_0ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_0MS)
}
#[doc = "Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms"]
#[inline(always)]
pub fn extclk_6ck_14ck_65ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTCLK_6CK_14CK_65MS)
}
#[doc = "PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 64 ms"]
#[inline(always)]
pub fn pllclk_1kck_14ck_64ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::PLLCLK_1KCK_14CK_64MS)
}
#[doc = "Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms"]
#[inline(always)]
pub fn intrcosc_8mhz_6ck_14ck_64ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_64MS)
}
#[doc = "ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms"]
#[inline(always)]
pub fn intrcosc_6mhz4_6ck_14ck_4ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::INTRCOSC_6MHZ4_6CK_14CK_4MS)
}
#[doc = "WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms"]
#[inline(always)]
pub fn wdosc_128khz_6ck_14ck_64ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_64MS)
}
#[doc = "Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 64 ms"]
#[inline(always)]
pub fn extlofxtal_32kck_14ck_64ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTLOFXTAL_32KCK_14CK_64MS)
}
#[doc = "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms"]
#[inline(always)]
pub fn extxosc_0mhz4_0mhz9_1kck_14ck_0ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS)
}
#[doc = "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms"]
#[inline(always)]
pub fn extxosc_0mhz4_0mhz9_16kck_14ck_4ms1(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1)
}
#[doc = "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms"]
#[inline(always)]
pub fn extxosc_0mhz9_3mhz_1kck_14ck_0ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS)
}
#[doc = "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms"]
#[inline(always)]
pub fn extxosc_0mhz9_3mhz_16kck_14ck_4ms1(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1)
}
#[doc = "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms"]
#[inline(always)]
pub fn extxosc_3mhz_8mhz_1kck_14ck_0ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS)
}
#[doc = "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms"]
#[inline(always)]
pub fn extxosc_3mhz_8mhz_16kck_14ck_4ms1(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1)
}
#[doc = "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms"]
#[inline(always)]
pub fn extxosc_8mhz_xx_1kck_14ck_0ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_0MS)
}
#[doc = "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms"]
#[inline(always)]
pub fn extxosc_8mhz_xx_16kck_14ck_4ms1(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1)
}
#[doc = "PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 64 ms"]
#[inline(always)]
pub fn pllclk_16kck_14ck_64ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::PLLCLK_16KCK_14CK_64MS)
}
#[doc = "ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 1 CK/14 CK + 0 ms"]
#[inline(always)]
pub fn intrcosc_6mhz4_1ck_14ck_0ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::INTRCOSC_6MHZ4_1CK_14CK_0MS)
}
#[doc = "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms"]
#[inline(always)]
pub fn extxosc_0mhz4_0mhz9_1kck_14ck_4ms1(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1)
}
#[doc = "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms"]
#[inline(always)]
pub fn extxosc_0mhz4_0mhz9_16kck_14ck_65ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS)
}
#[doc = "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms"]
#[inline(always)]
pub fn extxosc_0mhz9_3mhz_1kck_14ck_4ms1(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1)
}
#[doc = "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms"]
#[inline(always)]
pub fn extxosc_0mhz9_3mhz_16kck_14ck_65ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS)
}
#[doc = "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms"]
#[inline(always)]
pub fn extxosc_3mhz_8mhz_1kck_14ck_4ms1(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1)
}
#[doc = "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms"]
#[inline(always)]
pub fn extxosc_3mhz_8mhz_16kck_14ck_65ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS)
}
#[doc = "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms"]
#[inline(always)]
pub fn extxosc_8mhz_xx_1kck_14ck_4ms1(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1)
}
#[doc = "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms"]
#[inline(always)]
pub fn extxosc_8mhz_xx_16kck_14ck_65ms(self) -> &'a mut W {
self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_65MS)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !0x3f) | ((value as u8) & 0x3f);
self.w
}
}
#[doc = "Reader of field `CKOUT`"]
pub type CKOUT_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `CKOUT`"]
pub struct CKOUT_W<'a> {
w: &'a mut W,
}
impl<'a> CKOUT_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u8) & 0x01) << 6);
self.w
}
}
#[doc = "Reader of field `CKDIV8`"]
pub type CKDIV8_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `CKDIV8`"]
pub struct CKDIV8_W<'a> {
w: &'a mut W,
}
impl<'a> CKDIV8_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u8) & 0x01) << 7);
self.w
}
}
impl R {
#[doc = "Bits 0:5 - Select Clock source"]
#[inline(always)]
pub fn sut_cksel(&self) -> SUT_CKSEL_R {
SUT_CKSEL_R::new((self.bits & 0x3f) as u8)
}
#[doc = "Bit 6 - Clock output on PORTB4"]
#[inline(always)]
pub fn ckout(&self) -> CKOUT_R {
CKOUT_R::new(((self.bits >> 6) & 0x01) != 0)
}
#[doc = "Bit 7 - Divide clock by 8 internally"]
#[inline(always)]
pub fn ckdiv8(&self) -> CKDIV8_R {
CKDIV8_R::new(((self.bits >> 7) & 0x01) != 0)
}
}
impl W {
#[doc = "Bits 0:5 - Select Clock source"]
#[inline(always)]
pub fn sut_cksel(&mut self) -> SUT_CKSEL_W {
SUT_CKSEL_W { w: self }
}
#[doc = "Bit 6 - Clock output on PORTB4"]
#[inline(always)]
pub fn ckout(&mut self) -> CKOUT_W {
CKOUT_W { w: self }
}
#[doc = "Bit 7 - Divide clock by 8 internally"]
#[inline(always)]
pub fn ckdiv8(&mut self) -> CKDIV8_W {
CKDIV8_W { w: self }
}
}