1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62
#[doc = r"Value read from the register"] pub struct R { bits: u32, } impl super::RTC_IMR { #[doc = r"Reads the contents of the register"] #[inline(always)] pub fn read(&self) -> R { R { bits: self.register.get(), } } } #[doc = r"Reader of the field"] pub type ACK_R = crate::FR<bool, bool>; #[doc = r"Reader of the field"] pub type ALR_R = crate::FR<bool, bool>; #[doc = r"Reader of the field"] pub type SEC_R = crate::FR<bool, bool>; #[doc = r"Reader of the field"] pub type TIM_R = crate::FR<bool, bool>; #[doc = r"Reader of the field"] pub type CAL_R = crate::FR<bool, bool>; #[doc = r"Reader of the field"] pub type TDERR_R = crate::FR<bool, bool>; impl R { #[doc = r"Value of the register as raw bits"] #[inline(always)] pub fn bits(&self) -> u32 { self.bits } #[doc = "Bit 0 - Acknowledge Update Interrupt Mask"] #[inline(always)] pub fn ack(&self) -> ACK_R { ACK_R::new((self.bits() & 0x01) != 0) } #[doc = "Bit 1 - Alarm Interrupt Mask"] #[inline(always)] pub fn alr(&self) -> ALR_R { ALR_R::new(((self.bits() >> 1) & 0x01) != 0) } #[doc = "Bit 2 - Second Event Interrupt Mask"] #[inline(always)] pub fn sec(&self) -> SEC_R { SEC_R::new(((self.bits() >> 2) & 0x01) != 0) } #[doc = "Bit 3 - Time Event Interrupt Mask"] #[inline(always)] pub fn tim(&self) -> TIM_R { TIM_R::new(((self.bits() >> 3) & 0x01) != 0) } #[doc = "Bit 4 - Calendar Event Interrupt Mask"] #[inline(always)] pub fn cal(&self) -> CAL_R { CAL_R::new(((self.bits() >> 4) & 0x01) != 0) } #[doc = "Bit 5 - Time and/or Date Error Mask"] #[inline(always)] pub fn tderr(&self) -> TDERR_R { TDERR_R::new(((self.bits() >> 5) & 0x01) != 0) } }