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#[doc = r"Value read from the register"] pub struct R { bits: u32, } impl super::TWIHS_IMR { #[doc = r"Reads the contents of the register"] #[inline(always)] pub fn read(&self) -> R { R { bits: self.register.get(), } } } #[doc = r"Reader of the field"] pub type TXCOMP_R = crate::FR<bool, bool>; #[doc = r"Reader of the field"] pub type RXRDY_R = crate::FR<bool, bool>; #[doc = r"Reader of the field"] pub type TXRDY_R = crate::FR<bool, bool>; #[doc = r"Reader of the field"] pub type SVACC_R = crate::FR<bool, bool>; #[doc = r"Reader of the field"] pub type GACC_R = crate::FR<bool, bool>; #[doc = r"Reader of the field"] pub type OVRE_R = crate::FR<bool, bool>; #[doc = r"Reader of the field"] pub type UNRE_R = crate::FR<bool, bool>; #[doc = r"Reader of the field"] pub type NACK_R = crate::FR<bool, bool>; #[doc = r"Reader of the field"] pub type ARBLST_R = crate::FR<bool, bool>; #[doc = r"Reader of the field"] pub type SCL_WS_R = crate::FR<bool, bool>; #[doc = r"Reader of the field"] pub type EOSACC_R = crate::FR<bool, bool>; #[doc = r"Reader of the field"] pub type MCACK_R = crate::FR<bool, bool>; #[doc = r"Reader of the field"] pub type TOUT_R = crate::FR<bool, bool>; #[doc = r"Reader of the field"] pub type PECERR_R = crate::FR<bool, bool>; #[doc = r"Reader of the field"] pub type SMBDAM_R = crate::FR<bool, bool>; #[doc = r"Reader of the field"] pub type SMBHHM_R = crate::FR<bool, bool>; impl R { #[doc = r"Value of the register as raw bits"] #[inline(always)] pub fn bits(&self) -> u32 { self.bits } #[doc = "Bit 0 - Transmission Completed Interrupt Mask"] #[inline(always)] pub fn txcomp(&self) -> TXCOMP_R { TXCOMP_R::new((self.bits() & 0x01) != 0) } #[doc = "Bit 1 - Receive Holding Register Ready Interrupt Mask"] #[inline(always)] pub fn rxrdy(&self) -> RXRDY_R { RXRDY_R::new(((self.bits() >> 1) & 0x01) != 0) } #[doc = "Bit 2 - Transmit Holding Register Ready Interrupt Mask"] #[inline(always)] pub fn txrdy(&self) -> TXRDY_R { TXRDY_R::new(((self.bits() >> 2) & 0x01) != 0) } #[doc = "Bit 4 - Slave Access Interrupt Mask"] #[inline(always)] pub fn svacc(&self) -> SVACC_R { SVACC_R::new(((self.bits() >> 4) & 0x01) != 0) } #[doc = "Bit 5 - General Call Access Interrupt Mask"] #[inline(always)] pub fn gacc(&self) -> GACC_R { GACC_R::new(((self.bits() >> 5) & 0x01) != 0) } #[doc = "Bit 6 - Overrun Error Interrupt Mask"] #[inline(always)] pub fn ovre(&self) -> OVRE_R { OVRE_R::new(((self.bits() >> 6) & 0x01) != 0) } #[doc = "Bit 7 - Underrun Error Interrupt Mask"] #[inline(always)] pub fn unre(&self) -> UNRE_R { UNRE_R::new(((self.bits() >> 7) & 0x01) != 0) } #[doc = "Bit 8 - Not Acknowledge Interrupt Mask"] #[inline(always)] pub fn nack(&self) -> NACK_R { NACK_R::new(((self.bits() >> 8) & 0x01) != 0) } #[doc = "Bit 9 - Arbitration Lost Interrupt Mask"] #[inline(always)] pub fn arblst(&self) -> ARBLST_R { ARBLST_R::new(((self.bits() >> 9) & 0x01) != 0) } #[doc = "Bit 10 - Clock Wait State Interrupt Mask"] #[inline(always)] pub fn scl_ws(&self) -> SCL_WS_R { SCL_WS_R::new(((self.bits() >> 10) & 0x01) != 0) } #[doc = "Bit 11 - End Of Slave Access Interrupt Mask"] #[inline(always)] pub fn eosacc(&self) -> EOSACC_R { EOSACC_R::new(((self.bits() >> 11) & 0x01) != 0) } #[doc = "Bit 16 - Master Code Acknowledge Interrupt Mask"] #[inline(always)] pub fn mcack(&self) -> MCACK_R { MCACK_R::new(((self.bits() >> 16) & 0x01) != 0) } #[doc = "Bit 18 - Timeout Error Interrupt Mask"] #[inline(always)] pub fn tout(&self) -> TOUT_R { TOUT_R::new(((self.bits() >> 18) & 0x01) != 0) } #[doc = "Bit 19 - PEC Error Interrupt Mask"] #[inline(always)] pub fn pecerr(&self) -> PECERR_R { PECERR_R::new(((self.bits() >> 19) & 0x01) != 0) } #[doc = "Bit 20 - SMBus Default Address Match Interrupt Mask"] #[inline(always)] pub fn smbdam(&self) -> SMBDAM_R { SMBDAM_R::new(((self.bits() >> 20) & 0x01) != 0) } #[doc = "Bit 21 - SMBus Host Header Address Match Interrupt Mask"] #[inline(always)] pub fn smbhhm(&self) -> SMBHHM_R { SMBHHM_R::new(((self.bits() >> 21) & 0x01) != 0) } }