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#[doc = "Register `IDR` writer"]
pub struct W(crate::W<IDR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IDR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IDR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TXRDY` writer - Transmit Ready Interrupt Disable"]
pub struct TXRDY_W<'a> {
w: &'a mut W,
}
impl<'a> TXRDY_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}
#[doc = "Field `TXEMPTY` writer - Transmit Empty Interrupt Disable"]
pub struct TXEMPTY_W<'a> {
w: &'a mut W,
}
impl<'a> TXEMPTY_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
self.w
}
}
#[doc = "Field `RXRDY` writer - Receive Ready Interrupt Disable"]
pub struct RXRDY_W<'a> {
w: &'a mut W,
}
impl<'a> RXRDY_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
self.w
}
}
#[doc = "Field `OVRUN` writer - Receive Overrun Interrupt Disable"]
pub struct OVRUN_W<'a> {
w: &'a mut W,
}
impl<'a> OVRUN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
self.w
}
}
#[doc = "Field `CP0` writer - Compare 0 Interrupt Disable"]
pub struct CP0_W<'a> {
w: &'a mut W,
}
impl<'a> CP0_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
self.w
}
}
#[doc = "Field `CP1` writer - Compare 1 Interrupt Disable"]
pub struct CP1_W<'a> {
w: &'a mut W,
}
impl<'a> CP1_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
self.w
}
}
#[doc = "Field `TXSYN` writer - Tx Sync Interrupt Enable"]
pub struct TXSYN_W<'a> {
w: &'a mut W,
}
impl<'a> TXSYN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
self.w
}
}
#[doc = "Field `RXSYN` writer - Rx Sync Interrupt Enable"]
pub struct RXSYN_W<'a> {
w: &'a mut W,
}
impl<'a> RXSYN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
self.w
}
}
impl W {
#[doc = "Bit 0 - Transmit Ready Interrupt Disable"]
#[inline(always)]
pub fn txrdy(&mut self) -> TXRDY_W {
TXRDY_W { w: self }
}
#[doc = "Bit 1 - Transmit Empty Interrupt Disable"]
#[inline(always)]
pub fn txempty(&mut self) -> TXEMPTY_W {
TXEMPTY_W { w: self }
}
#[doc = "Bit 4 - Receive Ready Interrupt Disable"]
#[inline(always)]
pub fn rxrdy(&mut self) -> RXRDY_W {
RXRDY_W { w: self }
}
#[doc = "Bit 5 - Receive Overrun Interrupt Disable"]
#[inline(always)]
pub fn ovrun(&mut self) -> OVRUN_W {
OVRUN_W { w: self }
}
#[doc = "Bit 8 - Compare 0 Interrupt Disable"]
#[inline(always)]
pub fn cp0(&mut self) -> CP0_W {
CP0_W { w: self }
}
#[doc = "Bit 9 - Compare 1 Interrupt Disable"]
#[inline(always)]
pub fn cp1(&mut self) -> CP1_W {
CP1_W { w: self }
}
#[doc = "Bit 10 - Tx Sync Interrupt Enable"]
#[inline(always)]
pub fn txsyn(&mut self) -> TXSYN_W {
TXSYN_W { w: self }
}
#[doc = "Bit 11 - Rx Sync Interrupt Enable"]
#[inline(always)]
pub fn rxsyn(&mut self) -> RXSYN_W {
RXSYN_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"]
pub struct IDR_SPEC;
impl crate::RegisterSpec for IDR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"]
impl crate::Writable for IDR_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets IDR to value 0"]
impl crate::Resettable for IDR_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}
