1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229
#[doc = "Reader of register PVR[%s]"] pub type R = crate::R<u16, super::PVR>; #[doc = "Writer for register PVR[%s]"] pub type W = crate::W<u16, super::PVR>; #[doc = "Register PVR[%s] `reset()`'s with value 0"] impl crate::ResetValue for super::PVR { type Type = u16; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `SDCLKFSEL`"] pub type SDCLKFSEL_R = crate::R<u16, u16>; #[doc = "Write proxy for field `SDCLKFSEL`"] pub struct SDCLKFSEL_W<'a> { w: &'a mut W, } impl<'a> SDCLKFSEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u16) -> &'a mut W { self.w.bits = (self.w.bits & !0x03ff) | ((value as u16) & 0x03ff); self.w } } #[doc = "Clock Generator Select Value for Initialization\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CLKGSEL_A { #[doc = "0: Host Controller Ver2.00 Compatible Clock Generator (Divider)"] DIV = 0, #[doc = "1: Programmable Clock Generator"] PROG = 1, } impl From<CLKGSEL_A> for bool { #[inline(always)] fn from(variant: CLKGSEL_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `CLKGSEL`"] pub type CLKGSEL_R = crate::R<bool, CLKGSEL_A>; impl CLKGSEL_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> CLKGSEL_A { match self.bits { false => CLKGSEL_A::DIV, true => CLKGSEL_A::PROG, } } #[doc = "Checks if the value of the field is `DIV`"] #[inline(always)] pub fn is_div(&self) -> bool { *self == CLKGSEL_A::DIV } #[doc = "Checks if the value of the field is `PROG`"] #[inline(always)] pub fn is_prog(&self) -> bool { *self == CLKGSEL_A::PROG } } #[doc = "Write proxy for field `CLKGSEL`"] pub struct CLKGSEL_W<'a> { w: &'a mut W, } impl<'a> CLKGSEL_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: CLKGSEL_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Host Controller Ver2.00 Compatible Clock Generator (Divider)"] #[inline(always)] pub fn div(self) -> &'a mut W { self.variant(CLKGSEL_A::DIV) } #[doc = "Programmable Clock Generator"] #[inline(always)] pub fn prog(self) -> &'a mut W { self.variant(CLKGSEL_A::PROG) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u16) & 0x01) << 10); self.w } } #[doc = "Driver Strength Select Value for Initialization\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] #[repr(u8)] pub enum DRVSEL_A { #[doc = "0: Driver Type B is Selected"] B = 0, #[doc = "1: Driver Type A is Selected"] A = 1, #[doc = "2: Driver Type C is Selected"] C = 2, #[doc = "3: Driver Type D is Selected"] D = 3, } impl From<DRVSEL_A> for u8 { #[inline(always)] fn from(variant: DRVSEL_A) -> Self { variant as _ } } #[doc = "Reader of field `DRVSEL`"] pub type DRVSEL_R = crate::R<u8, DRVSEL_A>; impl DRVSEL_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> DRVSEL_A { match self.bits { 0 => DRVSEL_A::B, 1 => DRVSEL_A::A, 2 => DRVSEL_A::C, 3 => DRVSEL_A::D, _ => unreachable!(), } } #[doc = "Checks if the value of the field is `B`"] #[inline(always)] pub fn is_b(&self) -> bool { *self == DRVSEL_A::B } #[doc = "Checks if the value of the field is `A`"] #[inline(always)] pub fn is_a(&self) -> bool { *self == DRVSEL_A::A } #[doc = "Checks if the value of the field is `C`"] #[inline(always)] pub fn is_c(&self) -> bool { *self == DRVSEL_A::C } #[doc = "Checks if the value of the field is `D`"] #[inline(always)] pub fn is_d(&self) -> bool { *self == DRVSEL_A::D } } #[doc = "Write proxy for field `DRVSEL`"] pub struct DRVSEL_W<'a> { w: &'a mut W, } impl<'a> DRVSEL_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: DRVSEL_A) -> &'a mut W { { self.bits(variant.into()) } } #[doc = "Driver Type B is Selected"] #[inline(always)] pub fn b(self) -> &'a mut W { self.variant(DRVSEL_A::B) } #[doc = "Driver Type A is Selected"] #[inline(always)] pub fn a(self) -> &'a mut W { self.variant(DRVSEL_A::A) } #[doc = "Driver Type C is Selected"] #[inline(always)] pub fn c(self) -> &'a mut W { self.variant(DRVSEL_A::C) } #[doc = "Driver Type D is Selected"] #[inline(always)] pub fn d(self) -> &'a mut W { self.variant(DRVSEL_A::D) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u16) & 0x03) << 14); self.w } } impl R { #[doc = "Bits 0:9 - SDCLK Frequency Select Value for Initialization"] #[inline(always)] pub fn sdclkfsel(&self) -> SDCLKFSEL_R { SDCLKFSEL_R::new((self.bits & 0x03ff) as u16) } #[doc = "Bit 10 - Clock Generator Select Value for Initialization"] #[inline(always)] pub fn clkgsel(&self) -> CLKGSEL_R { CLKGSEL_R::new(((self.bits >> 10) & 0x01) != 0) } #[doc = "Bits 14:15 - Driver Strength Select Value for Initialization"] #[inline(always)] pub fn drvsel(&self) -> DRVSEL_R { DRVSEL_R::new(((self.bits >> 14) & 0x03) as u8) } } impl W { #[doc = "Bits 0:9 - SDCLK Frequency Select Value for Initialization"] #[inline(always)] pub fn sdclkfsel(&mut self) -> SDCLKFSEL_W { SDCLKFSEL_W { w: self } } #[doc = "Bit 10 - Clock Generator Select Value for Initialization"] #[inline(always)] pub fn clkgsel(&mut self) -> CLKGSEL_W { CLKGSEL_W { w: self } } #[doc = "Bits 14:15 - Driver Strength Select Value for Initialization"] #[inline(always)] pub fn drvsel(&mut self) -> DRVSEL_W { DRVSEL_W { w: self } } }