Module atsame53j20a_pac::gclk::genctrl[−][src]

Generic Clock Generator Control

Structs

DIVSEL_W	Write proxy for field `DIVSEL`
DIV_W	Write proxy for field `DIV`
GENEN_W	Write proxy for field `GENEN`
IDC_W	Write proxy for field `IDC`
OE_W	Write proxy for field `OE`
OOV_W	Write proxy for field `OOV`
RUNSTDBY_W	Write proxy for field `RUNSTDBY`
SRC_W	Write proxy for field `SRC`

DIVSEL_A	Divide Selection
SRC_A	Source Select

DIVSEL_R	Reader of field `DIVSEL`
DIV_R	Reader of field `DIV`
GENEN_R	Reader of field `GENEN`
IDC_R	Reader of field `IDC`
OE_R	Reader of field `OE`
OOV_R	Reader of field `OOV`
R	Reader of register GENCTRL[%s]
RUNSTDBY_R	Reader of field `RUNSTDBY`
SRC_R	Reader of field `SRC`
W	Writer for register GENCTRL[%s]