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#[doc = "Reader of register CCR"] pub type R = crate::R<u32, super::CCR>; #[doc = "Writer for register CCR"] pub type W = crate::W<u32, super::CCR>; #[doc = "Register CCR `reset()`'s with value 0x0200"] impl crate::ResetValue for super::CCR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0x0200 } } #[doc = "Reader of field `NONBASETHRDENA`"] pub type NONBASETHRDENA_R = crate::R<bool, bool>; #[doc = "Write proxy for field `NONBASETHRDENA`"] pub struct NONBASETHRDENA_W<'a> { w: &'a mut W, } impl<'a> NONBASETHRDENA_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); self.w } } #[doc = "Reader of field `USERSETMPEND`"] pub type USERSETMPEND_R = crate::R<bool, bool>; #[doc = "Write proxy for field `USERSETMPEND`"] pub struct USERSETMPEND_W<'a> { w: &'a mut W, } impl<'a> USERSETMPEND_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); self.w } } #[doc = "Enables unaligned access traps\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum UNALIGN_TRP_A { #[doc = "0: Do not trap unaligned halfword and word accesses"] VALUE_0 = 0, #[doc = "1: Trap unaligned halfword and word accesses"] VALUE_1 = 1, } impl From<UNALIGN_TRP_A> for bool { #[inline(always)] fn from(variant: UNALIGN_TRP_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `UNALIGN_TRP`"] pub type UNALIGN_TRP_R = crate::R<bool, UNALIGN_TRP_A>; impl UNALIGN_TRP_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> UNALIGN_TRP_A { match self.bits { false => UNALIGN_TRP_A::VALUE_0, true => UNALIGN_TRP_A::VALUE_1, } } #[doc = "Checks if the value of the field is `VALUE_0`"] #[inline(always)] pub fn is_value_0(&self) -> bool { *self == UNALIGN_TRP_A::VALUE_0 } #[doc = "Checks if the value of the field is `VALUE_1`"] #[inline(always)] pub fn is_value_1(&self) -> bool { *self == UNALIGN_TRP_A::VALUE_1 } } #[doc = "Write proxy for field `UNALIGN_TRP`"] pub struct UNALIGN_TRP_W<'a> { w: &'a mut W, } impl<'a> UNALIGN_TRP_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: UNALIGN_TRP_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Do not trap unaligned halfword and word accesses"] #[inline(always)] pub fn value_0(self) -> &'a mut W { self.variant(UNALIGN_TRP_A::VALUE_0) } #[doc = "Trap unaligned halfword and word accesses"] #[inline(always)] pub fn value_1(self) -> &'a mut W { self.variant(UNALIGN_TRP_A::VALUE_1) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); self.w } } #[doc = "Reader of field `DIV_0_TRP`"] pub type DIV_0_TRP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DIV_0_TRP`"] pub struct DIV_0_TRP_W<'a> { w: &'a mut W, } impl<'a> DIV_0_TRP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); self.w } } #[doc = "Reader of field `BFHFNMIGN`"] pub type BFHFNMIGN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `BFHFNMIGN`"] pub struct BFHFNMIGN_W<'a> { w: &'a mut W, } impl<'a> BFHFNMIGN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); self.w } } #[doc = "Indicates stack alignment on exception entry\n\nValue on reset: 1"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum STKALIGN_A { #[doc = "0: 4-byte aligned"] VALUE_0 = 0, #[doc = "1: 8-byte aligned"] VALUE_1 = 1, } impl From<STKALIGN_A> for bool { #[inline(always)] fn from(variant: STKALIGN_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `STKALIGN`"] pub type STKALIGN_R = crate::R<bool, STKALIGN_A>; impl STKALIGN_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> STKALIGN_A { match self.bits { false => STKALIGN_A::VALUE_0, true => STKALIGN_A::VALUE_1, } } #[doc = "Checks if the value of the field is `VALUE_0`"] #[inline(always)] pub fn is_value_0(&self) -> bool { *self == STKALIGN_A::VALUE_0 } #[doc = "Checks if the value of the field is `VALUE_1`"] #[inline(always)] pub fn is_value_1(&self) -> bool { *self == STKALIGN_A::VALUE_1 } } #[doc = "Write proxy for field `STKALIGN`"] pub struct STKALIGN_W<'a> { w: &'a mut W, } impl<'a> STKALIGN_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: STKALIGN_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "4-byte aligned"] #[inline(always)] pub fn value_0(self) -> &'a mut W { self.variant(STKALIGN_A::VALUE_0) } #[doc = "8-byte aligned"] #[inline(always)] pub fn value_1(self) -> &'a mut W { self.variant(STKALIGN_A::VALUE_1) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); self.w } } impl R { #[doc = "Bit 0 - Indicates how processor enters Thread mode"] #[inline(always)] pub fn nonbasethrdena(&self) -> NONBASETHRDENA_R { NONBASETHRDENA_R::new((self.bits & 0x01) != 0) } #[doc = "Bit 1 - Enables unprivileged software access to STIR register"] #[inline(always)] pub fn usersetmpend(&self) -> USERSETMPEND_R { USERSETMPEND_R::new(((self.bits >> 1) & 0x01) != 0) } #[doc = "Bit 3 - Enables unaligned access traps"] #[inline(always)] pub fn unalign_trp(&self) -> UNALIGN_TRP_R { UNALIGN_TRP_R::new(((self.bits >> 3) & 0x01) != 0) } #[doc = "Bit 4 - Enables divide by 0 trap"] #[inline(always)] pub fn div_0_trp(&self) -> DIV_0_TRP_R { DIV_0_TRP_R::new(((self.bits >> 4) & 0x01) != 0) } #[doc = "Bit 8 - Ignore LDM/STM BusFault for -1/-2 priority handlers"] #[inline(always)] pub fn bfhfnmign(&self) -> BFHFNMIGN_R { BFHFNMIGN_R::new(((self.bits >> 8) & 0x01) != 0) } #[doc = "Bit 9 - Indicates stack alignment on exception entry"] #[inline(always)] pub fn stkalign(&self) -> STKALIGN_R { STKALIGN_R::new(((self.bits >> 9) & 0x01) != 0) } } impl W { #[doc = "Bit 0 - Indicates how processor enters Thread mode"] #[inline(always)] pub fn nonbasethrdena(&mut self) -> NONBASETHRDENA_W { NONBASETHRDENA_W { w: self } } #[doc = "Bit 1 - Enables unprivileged software access to STIR register"] #[inline(always)] pub fn usersetmpend(&mut self) -> USERSETMPEND_W { USERSETMPEND_W { w: self } } #[doc = "Bit 3 - Enables unaligned access traps"] #[inline(always)] pub fn unalign_trp(&mut self) -> UNALIGN_TRP_W { UNALIGN_TRP_W { w: self } } #[doc = "Bit 4 - Enables divide by 0 trap"] #[inline(always)] pub fn div_0_trp(&mut self) -> DIV_0_TRP_W { DIV_0_TRP_W { w: self } } #[doc = "Bit 8 - Ignore LDM/STM BusFault for -1/-2 priority handlers"] #[inline(always)] pub fn bfhfnmign(&mut self) -> BFHFNMIGN_W { BFHFNMIGN_W { w: self } } #[doc = "Bit 9 - Indicates stack alignment on exception entry"] #[inline(always)] pub fn stkalign(&mut self) -> STKALIGN_W { STKALIGN_W { w: self } } }