[−][src]Module atsamd51j20a::dmac
Direct Memory Access Controller
Modules
active | Active Channel and Levels |
baseaddr | Descriptor Memory Section Base Address |
busych | Busy Channels |
chctrla | Channel n Control A |
chctrlb | Channel n Control B |
chevctrl | Channel n Event Control |
chintenclr | Channel n Interrupt Enable Clear |
chintenset | Channel n Interrupt Enable Set |
chintflag | Channel n Interrupt Flag Status and Clear |
chprilvl | Channel n Priority Level |
chstatus | Channel n Status |
crcchksum | CRC Checksum |
crcctrl | CRC Control |
crcdatain | CRC Data Input |
crcstatus | CRC Status |
ctrl | Control |
dbgctrl | Debug Control |
intpend | Interrupt Pending |
intstatus | Interrupt Status |
pendch | Pending Channels |
prictrl0 | Priority Control 0 |
swtrigctrl | Software Trigger Control |
wrbaddr | Write-Back Memory Section Base Address |
Structs
ACTIVE | Active Channel and Levels |
BASEADDR | Descriptor Memory Section Base Address |
BUSYCH | Busy Channels |
CHCTRLA | Channel n Control A |
CHCTRLB | Channel n Control B |
CHEVCTRL | Channel n Event Control |
CHINTENCLR | Channel n Interrupt Enable Clear |
CHINTENSET | Channel n Interrupt Enable Set |
CHINTFLAG | Channel n Interrupt Flag Status and Clear |
CHPRILVL | Channel n Priority Level |
CHSTATUS | Channel n Status |
CRCCHKSUM | CRC Checksum |
CRCCTRL | CRC Control |
CRCDATAIN | CRC Data Input |
CRCSTATUS | CRC Status |
CTRL | Control |
DBGCTRL | Debug Control |
INTPEND | Interrupt Pending |
INTSTATUS | Interrupt Status |
PENDCH | Pending Channels |
PRICTRL0 | Priority Control 0 |
RegisterBlock | Register block |
SWTRIGCTRL | Software Trigger Control |
WRBADDR | Write-Back Memory Section Base Address |