Module atsamd51j::dmac

Direct Memory Access Controller

Modules

active	Active Channel and Levels
baseaddr	Descriptor Memory Section Base Address
busych	Busy Channels
channel	Register block CHANNEL[%s]
crcchksum	CRC Checksum
crcctrl	CRC Control
crcdatain	CRC Data Input
crcstatus	CRC Status
ctrl	Control
dbgctrl	Debug Control
intpend	Interrupt Pending
intstatus	Interrupt Status
pendch	Pending Channels
prictrl0	Priority Control 0
swtrigctrl	Software Trigger Control
wrbaddr	Write-Back Memory Section Base Address

Structs

CHANNEL	Register block
RegisterBlock	Register block

Type Definitions

ACTIVE	Active Channel and Levels
BASEADDR	Descriptor Memory Section Base Address
BUSYCH	Busy Channels
CRCCHKSUM	CRC Checksum
CRCCTRL	CRC Control
CRCDATAIN	CRC Data Input
CRCSTATUS	CRC Status
CTRL	Control
DBGCTRL	Debug Control
INTPEND	Interrupt Pending
INTSTATUS	Interrupt Status
PENDCH	Pending Channels
PRICTRL0	Priority Control 0
SWTRIGCTRL	Software Trigger Control
WRBADDR	Write-Back Memory Section Base Address