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#[doc = "Reader of register INTENCLR"] pub type R = crate::R<u16, super::INTENCLR>; #[doc = "Writer for register INTENCLR"] pub type W = crate::W<u16, super::INTENCLR>; #[doc = "Register INTENCLR `reset()`'s with value 0"] impl crate::ResetValue for super::INTENCLR { type Type = u16; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `HSOF`"] pub type HSOF_R = crate::R<bool, bool>; #[doc = "Write proxy for field `HSOF`"] pub struct HSOF_W<'a> { w: &'a mut W, } impl<'a> HSOF_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u16) & 0x01) << 2); self.w } } #[doc = "Reader of field `RST`"] pub type RST_R = crate::R<bool, bool>; #[doc = "Write proxy for field `RST`"] pub struct RST_W<'a> { w: &'a mut W, } impl<'a> RST_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u16) & 0x01) << 3); self.w } } #[doc = "Reader of field `WAKEUP`"] pub type WAKEUP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `WAKEUP`"] pub struct WAKEUP_W<'a> { w: &'a mut W, } impl<'a> WAKEUP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u16) & 0x01) << 4); self.w } } #[doc = "Reader of field `DNRSM`"] pub type DNRSM_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DNRSM`"] pub struct DNRSM_W<'a> { w: &'a mut W, } impl<'a> DNRSM_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u16) & 0x01) << 5); self.w } } #[doc = "Reader of field `UPRSM`"] pub type UPRSM_R = crate::R<bool, bool>; #[doc = "Write proxy for field `UPRSM`"] pub struct UPRSM_W<'a> { w: &'a mut W, } impl<'a> UPRSM_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u16) & 0x01) << 6); self.w } } #[doc = "Reader of field `RAMACER`"] pub type RAMACER_R = crate::R<bool, bool>; #[doc = "Write proxy for field `RAMACER`"] pub struct RAMACER_W<'a> { w: &'a mut W, } impl<'a> RAMACER_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u16) & 0x01) << 7); self.w } } #[doc = "Reader of field `DCONN`"] pub type DCONN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DCONN`"] pub struct DCONN_W<'a> { w: &'a mut W, } impl<'a> DCONN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u16) & 0x01) << 8); self.w } } #[doc = "Reader of field `DDISC`"] pub type DDISC_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DDISC`"] pub struct DDISC_W<'a> { w: &'a mut W, } impl<'a> DDISC_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u16) & 0x01) << 9); self.w } } impl R { #[doc = "Bit 2 - Host Start Of Frame Interrupt Disable"] #[inline(always)] pub fn hsof(&self) -> HSOF_R { HSOF_R::new(((self.bits >> 2) & 0x01) != 0) } #[doc = "Bit 3 - BUS Reset Interrupt Disable"] #[inline(always)] pub fn rst(&self) -> RST_R { RST_R::new(((self.bits >> 3) & 0x01) != 0) } #[doc = "Bit 4 - Wake Up Interrupt Disable"] #[inline(always)] pub fn wakeup(&self) -> WAKEUP_R { WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0) } #[doc = "Bit 5 - DownStream to Device Interrupt Disable"] #[inline(always)] pub fn dnrsm(&self) -> DNRSM_R { DNRSM_R::new(((self.bits >> 5) & 0x01) != 0) } #[doc = "Bit 6 - Upstream Resume from Device Interrupt Disable"] #[inline(always)] pub fn uprsm(&self) -> UPRSM_R { UPRSM_R::new(((self.bits >> 6) & 0x01) != 0) } #[doc = "Bit 7 - Ram Access Interrupt Disable"] #[inline(always)] pub fn ramacer(&self) -> RAMACER_R { RAMACER_R::new(((self.bits >> 7) & 0x01) != 0) } #[doc = "Bit 8 - Device Connection Interrupt Disable"] #[inline(always)] pub fn dconn(&self) -> DCONN_R { DCONN_R::new(((self.bits >> 8) & 0x01) != 0) } #[doc = "Bit 9 - Device Disconnection Interrupt Disable"] #[inline(always)] pub fn ddisc(&self) -> DDISC_R { DDISC_R::new(((self.bits >> 9) & 0x01) != 0) } } impl W { #[doc = "Bit 2 - Host Start Of Frame Interrupt Disable"] #[inline(always)] pub fn hsof(&mut self) -> HSOF_W { HSOF_W { w: self } } #[doc = "Bit 3 - BUS Reset Interrupt Disable"] #[inline(always)] pub fn rst(&mut self) -> RST_W { RST_W { w: self } } #[doc = "Bit 4 - Wake Up Interrupt Disable"] #[inline(always)] pub fn wakeup(&mut self) -> WAKEUP_W { WAKEUP_W { w: self } } #[doc = "Bit 5 - DownStream to Device Interrupt Disable"] #[inline(always)] pub fn dnrsm(&mut self) -> DNRSM_W { DNRSM_W { w: self } } #[doc = "Bit 6 - Upstream Resume from Device Interrupt Disable"] #[inline(always)] pub fn uprsm(&mut self) -> UPRSM_W { UPRSM_W { w: self } } #[doc = "Bit 7 - Ram Access Interrupt Disable"] #[inline(always)] pub fn ramacer(&mut self) -> RAMACER_W { RAMACER_W { w: self } } #[doc = "Bit 8 - Device Connection Interrupt Disable"] #[inline(always)] pub fn dconn(&mut self) -> DCONN_W { DCONN_W { w: self } } #[doc = "Bit 9 - Device Disconnection Interrupt Disable"] #[inline(always)] pub fn ddisc(&mut self) -> DDISC_W { DDISC_W { w: self } } }