Module atsamd11c::dmac

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Direct Memory Access Controller

Modules§

Structs§

Type Aliases§

  • ACTIVE
    ACTIVE (r) register accessor: Active Channel and Levels
  • BASEADDR
    BASEADDR (rw) register accessor: Descriptor Memory Section Base Address
  • BUSYCH
    BUSYCH (r) register accessor: Busy Channels
  • CHCTRLA
    CHCTRLA (rw) register accessor: Channel Control A
  • CHCTRLB
    CHCTRLB (rw) register accessor: Channel Control B
  • CHID
    CHID (rw) register accessor: Channel ID
  • CHINTENCLR
    CHINTENCLR (rw) register accessor: Channel Interrupt Enable Clear
  • CHINTENSET
    CHINTENSET (rw) register accessor: Channel Interrupt Enable Set
  • CHINTFLAG
    CHINTFLAG (rw) register accessor: Channel Interrupt Flag Status and Clear
  • CHSTATUS
    CHSTATUS (r) register accessor: Channel Status
  • CRCCHKSUM
    CRCCHKSUM (rw) register accessor: CRC Checksum
  • CRCCTRL
    CRCCTRL (rw) register accessor: CRC Control
  • CRCDATAIN
    CRCDATAIN (rw) register accessor: CRC Data Input
  • CRCSTATUS
    CRCSTATUS (rw) register accessor: CRC Status
  • CTRL
    CTRL (rw) register accessor: Control
  • DBGCTRL
    DBGCTRL (rw) register accessor: Debug Control
  • INTPEND
    INTPEND (rw) register accessor: Interrupt Pending
  • INTSTATUS
    INTSTATUS (r) register accessor: Interrupt Status
  • PENDCH
    PENDCH (r) register accessor: Pending Channels
  • PRICTRL0
    PRICTRL0 (rw) register accessor: Priority Control 0
  • QOSCTRL
    QOSCTRL (rw) register accessor: QOS Control
  • SWTRIGCTRL
    SWTRIGCTRL (rw) register accessor: Software Trigger Control
  • WRBADDR
    WRBADDR (rw) register accessor: Write-Back Memory Section Base Address