Module atsam4sa16b_pac::tc0[][src]

Timer Counter 0

Modules

bcr

Block Control Register

bmr

Block Mode Register

ccr0

Channel Control Register (channel = 0)

ccr1

Channel Control Register (channel = 1)

ccr2

Channel Control Register (channel = 2)

cmr0

Channel Mode Register (channel = 0)

cmr0_wave_eq_1

Channel Mode Register (channel = 0)

cmr1

Channel Mode Register (channel = 1)

cmr1_wave_eq_1

Channel Mode Register (channel = 1)

cmr2

Channel Mode Register (channel = 2)

cmr2_wave_eq_1

Channel Mode Register (channel = 2)

cv0

Counter Value (channel = 0)

cv1

Counter Value (channel = 1)

cv2

Counter Value (channel = 2)

fmr

Fault Mode Register

idr0

Interrupt Disable Register (channel = 0)

idr1

Interrupt Disable Register (channel = 1)

idr2

Interrupt Disable Register (channel = 2)

ier0

Interrupt Enable Register (channel = 0)

ier1

Interrupt Enable Register (channel = 1)

ier2

Interrupt Enable Register (channel = 2)

imr0

Interrupt Mask Register (channel = 0)

imr1

Interrupt Mask Register (channel = 1)

imr2

Interrupt Mask Register (channel = 2)

qidr

QDEC Interrupt Disable Register

qier

QDEC Interrupt Enable Register

qimr

QDEC Interrupt Mask Register

qisr

QDEC Interrupt Status Register

ra0

Register A (channel = 0)

ra1

Register A (channel = 1)

ra2

Register A (channel = 2)

rb0

Register B (channel = 0)

rb1

Register B (channel = 1)

rb2

Register B (channel = 2)

rc0

Register C (channel = 0)

rc1

Register C (channel = 1)

rc2

Register C (channel = 2)

smmr0

Stepper Motor Mode Register (channel = 0)

smmr1

Stepper Motor Mode Register (channel = 1)

smmr2

Stepper Motor Mode Register (channel = 2)

sr0

Status Register (channel = 0)

sr1

Status Register (channel = 1)

sr2

Status Register (channel = 2)

wpmr

Write Protection Mode Register

Structs

RegisterBlock

Register block

Type Definitions

BCR

Block Control Register

BMR

Block Mode Register

CCR0

Channel Control Register (channel = 0)

CCR1

Channel Control Register (channel = 1)

CCR2

Channel Control Register (channel = 2)

CMR0

Channel Mode Register (channel = 0)

CMR0_WAVE_EQ_1

Channel Mode Register (channel = 0)

CMR1

Channel Mode Register (channel = 1)

CMR1_WAVE_EQ_1

Channel Mode Register (channel = 1)

CMR2

Channel Mode Register (channel = 2)

CMR2_WAVE_EQ_1

Channel Mode Register (channel = 2)

CV0

Counter Value (channel = 0)

CV1

Counter Value (channel = 1)

CV2

Counter Value (channel = 2)

FMR

Fault Mode Register

IDR0

Interrupt Disable Register (channel = 0)

IDR1

Interrupt Disable Register (channel = 1)

IDR2

Interrupt Disable Register (channel = 2)

IER0

Interrupt Enable Register (channel = 0)

IER1

Interrupt Enable Register (channel = 1)

IER2

Interrupt Enable Register (channel = 2)

IMR0

Interrupt Mask Register (channel = 0)

IMR1

Interrupt Mask Register (channel = 1)

IMR2

Interrupt Mask Register (channel = 2)

QIDR

QDEC Interrupt Disable Register

QIER

QDEC Interrupt Enable Register

QIMR

QDEC Interrupt Mask Register

QISR

QDEC Interrupt Status Register

RA0

Register A (channel = 0)

RA1

Register A (channel = 1)

RA2

Register A (channel = 2)

RB0

Register B (channel = 0)

RB1

Register B (channel = 1)

RB2

Register B (channel = 2)

RC0

Register C (channel = 0)

RC1

Register C (channel = 1)

RC2

Register C (channel = 2)

SMMR0

Stepper Motor Mode Register (channel = 0)

SMMR1

Stepper Motor Mode Register (channel = 1)

SMMR2

Stepper Motor Mode Register (channel = 2)

SR0

Status Register (channel = 0)

SR1

Status Register (channel = 1)

SR2

Status Register (channel = 2)

WPMR

Write Protection Mode Register