Module atsam4s4b_pac::tc0

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Expand description

Timer Counter 0

Modules

  • bcr
    Block Control Register
  • bmr
    Block Mode Register
  • ccr0
    Channel Control Register (channel = 0)
  • ccr1
    Channel Control Register (channel = 1)
  • ccr2
    Channel Control Register (channel = 2)
  • cmr0
    Channel Mode Register (channel = 0)
  • cmr1
    Channel Mode Register (channel = 1)
  • cmr2
    Channel Mode Register (channel = 2)
  • cv0
    Counter Value (channel = 0)
  • cv1
    Counter Value (channel = 1)
  • cv2
    Counter Value (channel = 2)
  • fmr
    Fault Mode Register
  • idr0
    Interrupt Disable Register (channel = 0)
  • idr1
    Interrupt Disable Register (channel = 1)
  • idr2
    Interrupt Disable Register (channel = 2)
  • ier0
    Interrupt Enable Register (channel = 0)
  • ier1
    Interrupt Enable Register (channel = 1)
  • ier2
    Interrupt Enable Register (channel = 2)
  • imr0
    Interrupt Mask Register (channel = 0)
  • imr1
    Interrupt Mask Register (channel = 1)
  • imr2
    Interrupt Mask Register (channel = 2)
  • qidr
    QDEC Interrupt Disable Register
  • qier
    QDEC Interrupt Enable Register
  • qimr
    QDEC Interrupt Mask Register
  • qisr
    QDEC Interrupt Status Register
  • ra0
    Register A (channel = 0)
  • ra1
    Register A (channel = 1)
  • ra2
    Register A (channel = 2)
  • rb0
    Register B (channel = 0)
  • rb1
    Register B (channel = 1)
  • rb2
    Register B (channel = 2)
  • rc0
    Register C (channel = 0)
  • rc1
    Register C (channel = 1)
  • rc2
    Register C (channel = 2)
  • smmr0
    Stepper Motor Mode Register (channel = 0)
  • smmr1
    Stepper Motor Mode Register (channel = 1)
  • smmr2
    Stepper Motor Mode Register (channel = 2)
  • sr0
    Status Register (channel = 0)
  • sr1
    Status Register (channel = 1)
  • sr2
    Status Register (channel = 2)
  • wave_eq_1_cmr0_wave_eq_1
    Channel Mode Register (channel = 0)
  • wave_eq_1_cmr1_wave_eq_1
    Channel Mode Register (channel = 1)
  • wave_eq_1_cmr2_wave_eq_1
    Channel Mode Register (channel = 2)
  • wpmr
    Write Protection Mode Register

Structs

Type Definitions

  • BCR
    BCR (w) register accessor: an alias for Reg<BCR_SPEC>
  • BMR
    BMR (rw) register accessor: an alias for Reg<BMR_SPEC>
  • CCR0
    CCR0 (w) register accessor: an alias for Reg<CCR0_SPEC>
  • CCR1
    CCR1 (w) register accessor: an alias for Reg<CCR1_SPEC>
  • CCR2
    CCR2 (w) register accessor: an alias for Reg<CCR2_SPEC>
  • CMR0
    CMR0 (rw) register accessor: an alias for Reg<CMR0_SPEC>
  • CMR1
    CMR1 (rw) register accessor: an alias for Reg<CMR1_SPEC>
  • CMR2
    CMR2 (rw) register accessor: an alias for Reg<CMR2_SPEC>
  • CV0
    CV0 (r) register accessor: an alias for Reg<CV0_SPEC>
  • CV1
    CV1 (r) register accessor: an alias for Reg<CV1_SPEC>
  • CV2
    CV2 (r) register accessor: an alias for Reg<CV2_SPEC>
  • FMR
    FMR (rw) register accessor: an alias for Reg<FMR_SPEC>
  • IDR0
    IDR0 (w) register accessor: an alias for Reg<IDR0_SPEC>
  • IDR1
    IDR1 (w) register accessor: an alias for Reg<IDR1_SPEC>
  • IDR2
    IDR2 (w) register accessor: an alias for Reg<IDR2_SPEC>
  • IER0
    IER0 (w) register accessor: an alias for Reg<IER0_SPEC>
  • IER1
    IER1 (w) register accessor: an alias for Reg<IER1_SPEC>
  • IER2
    IER2 (w) register accessor: an alias for Reg<IER2_SPEC>
  • IMR0
    IMR0 (r) register accessor: an alias for Reg<IMR0_SPEC>
  • IMR1
    IMR1 (r) register accessor: an alias for Reg<IMR1_SPEC>
  • IMR2
    IMR2 (r) register accessor: an alias for Reg<IMR2_SPEC>
  • QIDR
    QIDR (w) register accessor: an alias for Reg<QIDR_SPEC>
  • QIER
    QIER (w) register accessor: an alias for Reg<QIER_SPEC>
  • QIMR
    QIMR (r) register accessor: an alias for Reg<QIMR_SPEC>
  • QISR
    QISR (r) register accessor: an alias for Reg<QISR_SPEC>
  • RA0
    RA0 (rw) register accessor: an alias for Reg<RA0_SPEC>
  • RA1
    RA1 (rw) register accessor: an alias for Reg<RA1_SPEC>
  • RA2
    RA2 (rw) register accessor: an alias for Reg<RA2_SPEC>
  • RB0
    RB0 (rw) register accessor: an alias for Reg<RB0_SPEC>
  • RB1
    RB1 (rw) register accessor: an alias for Reg<RB1_SPEC>
  • RB2
    RB2 (rw) register accessor: an alias for Reg<RB2_SPEC>
  • RC0
    RC0 (rw) register accessor: an alias for Reg<RC0_SPEC>
  • RC1
    RC1 (rw) register accessor: an alias for Reg<RC1_SPEC>
  • RC2
    RC2 (rw) register accessor: an alias for Reg<RC2_SPEC>
  • SMMR0
    SMMR0 (rw) register accessor: an alias for Reg<SMMR0_SPEC>
  • SMMR1
    SMMR1 (rw) register accessor: an alias for Reg<SMMR1_SPEC>
  • SMMR2
    SMMR2 (rw) register accessor: an alias for Reg<SMMR2_SPEC>
  • SR0
    SR0 (r) register accessor: an alias for Reg<SR0_SPEC>
  • SR1
    SR1 (r) register accessor: an alias for Reg<SR1_SPEC>
  • SR2
    SR2 (r) register accessor: an alias for Reg<SR2_SPEC>
  • WAVE_EQ_1_CMR0_WAVE_EQ_1
    WAVE_EQ_1_CMR0_WAVE_EQ_1 (rw) register accessor: an alias for Reg<WAVE_EQ_1_CMR0_WAVE_EQ_1_SPEC>
  • WAVE_EQ_1_CMR1_WAVE_EQ_1
    WAVE_EQ_1_CMR1_WAVE_EQ_1 (rw) register accessor: an alias for Reg<WAVE_EQ_1_CMR1_WAVE_EQ_1_SPEC>
  • WAVE_EQ_1_CMR2_WAVE_EQ_1
    WAVE_EQ_1_CMR2_WAVE_EQ_1 (rw) register accessor: an alias for Reg<WAVE_EQ_1_CMR2_WAVE_EQ_1_SPEC>
  • WPMR
    WPMR (rw) register accessor: an alias for Reg<WPMR_SPEC>