1#[doc = "Register `BMR` reader"]
2pub struct R(crate::R<BMR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<BMR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<BMR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<BMR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `BMR` writer"]
17pub struct W(crate::W<BMR_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<BMR_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<BMR_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<BMR_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `TC0XC0S` reader - External Clock Signal 0 Selection"]
38pub type TC0XC0S_R = crate::FieldReader<u8, TC0XC0S_A>;
39#[doc = "External Clock Signal 0 Selection\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum TC0XC0S_A {
43 #[doc = "0: Signal connected to XC0: TCLK0"]
44 TCLK0 = 0,
45 #[doc = "2: Signal connected to XC0: TIOA1"]
46 TIOA1 = 2,
47 #[doc = "3: Signal connected to XC0: TIOA2"]
48 TIOA2 = 3,
49}
50impl From<TC0XC0S_A> for u8 {
51 #[inline(always)]
52 fn from(variant: TC0XC0S_A) -> Self {
53 variant as _
54 }
55}
56impl TC0XC0S_R {
57 #[doc = "Get enumerated values variant"]
58 #[inline(always)]
59 pub fn variant(&self) -> Option<TC0XC0S_A> {
60 match self.bits {
61 0 => Some(TC0XC0S_A::TCLK0),
62 2 => Some(TC0XC0S_A::TIOA1),
63 3 => Some(TC0XC0S_A::TIOA2),
64 _ => None,
65 }
66 }
67 #[doc = "Checks if the value of the field is `TCLK0`"]
68 #[inline(always)]
69 pub fn is_tclk0(&self) -> bool {
70 *self == TC0XC0S_A::TCLK0
71 }
72 #[doc = "Checks if the value of the field is `TIOA1`"]
73 #[inline(always)]
74 pub fn is_tioa1(&self) -> bool {
75 *self == TC0XC0S_A::TIOA1
76 }
77 #[doc = "Checks if the value of the field is `TIOA2`"]
78 #[inline(always)]
79 pub fn is_tioa2(&self) -> bool {
80 *self == TC0XC0S_A::TIOA2
81 }
82}
83#[doc = "Field `TC0XC0S` writer - External Clock Signal 0 Selection"]
84pub type TC0XC0S_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BMR_SPEC, u8, TC0XC0S_A, 2, O>;
85impl<'a, const O: u8> TC0XC0S_W<'a, O> {
86 #[doc = "Signal connected to XC0: TCLK0"]
87 #[inline(always)]
88 pub fn tclk0(self) -> &'a mut W {
89 self.variant(TC0XC0S_A::TCLK0)
90 }
91 #[doc = "Signal connected to XC0: TIOA1"]
92 #[inline(always)]
93 pub fn tioa1(self) -> &'a mut W {
94 self.variant(TC0XC0S_A::TIOA1)
95 }
96 #[doc = "Signal connected to XC0: TIOA2"]
97 #[inline(always)]
98 pub fn tioa2(self) -> &'a mut W {
99 self.variant(TC0XC0S_A::TIOA2)
100 }
101}
102#[doc = "Field `TC1XC1S` reader - External Clock Signal 1 Selection"]
103pub type TC1XC1S_R = crate::FieldReader<u8, TC1XC1S_A>;
104#[doc = "External Clock Signal 1 Selection\n\nValue on reset: 0"]
105#[derive(Clone, Copy, Debug, PartialEq, Eq)]
106#[repr(u8)]
107pub enum TC1XC1S_A {
108 #[doc = "0: Signal connected to XC1: TCLK1"]
109 TCLK1 = 0,
110 #[doc = "2: Signal connected to XC1: TIOA0"]
111 TIOA0 = 2,
112 #[doc = "3: Signal connected to XC1: TIOA2"]
113 TIOA2 = 3,
114}
115impl From<TC1XC1S_A> for u8 {
116 #[inline(always)]
117 fn from(variant: TC1XC1S_A) -> Self {
118 variant as _
119 }
120}
121impl TC1XC1S_R {
122 #[doc = "Get enumerated values variant"]
123 #[inline(always)]
124 pub fn variant(&self) -> Option<TC1XC1S_A> {
125 match self.bits {
126 0 => Some(TC1XC1S_A::TCLK1),
127 2 => Some(TC1XC1S_A::TIOA0),
128 3 => Some(TC1XC1S_A::TIOA2),
129 _ => None,
130 }
131 }
132 #[doc = "Checks if the value of the field is `TCLK1`"]
133 #[inline(always)]
134 pub fn is_tclk1(&self) -> bool {
135 *self == TC1XC1S_A::TCLK1
136 }
137 #[doc = "Checks if the value of the field is `TIOA0`"]
138 #[inline(always)]
139 pub fn is_tioa0(&self) -> bool {
140 *self == TC1XC1S_A::TIOA0
141 }
142 #[doc = "Checks if the value of the field is `TIOA2`"]
143 #[inline(always)]
144 pub fn is_tioa2(&self) -> bool {
145 *self == TC1XC1S_A::TIOA2
146 }
147}
148#[doc = "Field `TC1XC1S` writer - External Clock Signal 1 Selection"]
149pub type TC1XC1S_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BMR_SPEC, u8, TC1XC1S_A, 2, O>;
150impl<'a, const O: u8> TC1XC1S_W<'a, O> {
151 #[doc = "Signal connected to XC1: TCLK1"]
152 #[inline(always)]
153 pub fn tclk1(self) -> &'a mut W {
154 self.variant(TC1XC1S_A::TCLK1)
155 }
156 #[doc = "Signal connected to XC1: TIOA0"]
157 #[inline(always)]
158 pub fn tioa0(self) -> &'a mut W {
159 self.variant(TC1XC1S_A::TIOA0)
160 }
161 #[doc = "Signal connected to XC1: TIOA2"]
162 #[inline(always)]
163 pub fn tioa2(self) -> &'a mut W {
164 self.variant(TC1XC1S_A::TIOA2)
165 }
166}
167#[doc = "Field `TC2XC2S` reader - External Clock Signal 2 Selection"]
168pub type TC2XC2S_R = crate::FieldReader<u8, TC2XC2S_A>;
169#[doc = "External Clock Signal 2 Selection\n\nValue on reset: 0"]
170#[derive(Clone, Copy, Debug, PartialEq, Eq)]
171#[repr(u8)]
172pub enum TC2XC2S_A {
173 #[doc = "0: Signal connected to XC2: TCLK2"]
174 TCLK2 = 0,
175 #[doc = "2: Signal connected to XC2: TIOA1"]
176 TIOA1 = 2,
177 #[doc = "3: Signal connected to XC2: TIOA2"]
178 TIOA2 = 3,
179}
180impl From<TC2XC2S_A> for u8 {
181 #[inline(always)]
182 fn from(variant: TC2XC2S_A) -> Self {
183 variant as _
184 }
185}
186impl TC2XC2S_R {
187 #[doc = "Get enumerated values variant"]
188 #[inline(always)]
189 pub fn variant(&self) -> Option<TC2XC2S_A> {
190 match self.bits {
191 0 => Some(TC2XC2S_A::TCLK2),
192 2 => Some(TC2XC2S_A::TIOA1),
193 3 => Some(TC2XC2S_A::TIOA2),
194 _ => None,
195 }
196 }
197 #[doc = "Checks if the value of the field is `TCLK2`"]
198 #[inline(always)]
199 pub fn is_tclk2(&self) -> bool {
200 *self == TC2XC2S_A::TCLK2
201 }
202 #[doc = "Checks if the value of the field is `TIOA1`"]
203 #[inline(always)]
204 pub fn is_tioa1(&self) -> bool {
205 *self == TC2XC2S_A::TIOA1
206 }
207 #[doc = "Checks if the value of the field is `TIOA2`"]
208 #[inline(always)]
209 pub fn is_tioa2(&self) -> bool {
210 *self == TC2XC2S_A::TIOA2
211 }
212}
213#[doc = "Field `TC2XC2S` writer - External Clock Signal 2 Selection"]
214pub type TC2XC2S_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BMR_SPEC, u8, TC2XC2S_A, 2, O>;
215impl<'a, const O: u8> TC2XC2S_W<'a, O> {
216 #[doc = "Signal connected to XC2: TCLK2"]
217 #[inline(always)]
218 pub fn tclk2(self) -> &'a mut W {
219 self.variant(TC2XC2S_A::TCLK2)
220 }
221 #[doc = "Signal connected to XC2: TIOA1"]
222 #[inline(always)]
223 pub fn tioa1(self) -> &'a mut W {
224 self.variant(TC2XC2S_A::TIOA1)
225 }
226 #[doc = "Signal connected to XC2: TIOA2"]
227 #[inline(always)]
228 pub fn tioa2(self) -> &'a mut W {
229 self.variant(TC2XC2S_A::TIOA2)
230 }
231}
232#[doc = "Field `QDEN` reader - Quadrature Decoder ENabled"]
233pub type QDEN_R = crate::BitReader<bool>;
234#[doc = "Field `QDEN` writer - Quadrature Decoder ENabled"]
235pub type QDEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, BMR_SPEC, bool, O>;
236#[doc = "Field `POSEN` reader - POSition ENabled"]
237pub type POSEN_R = crate::BitReader<bool>;
238#[doc = "Field `POSEN` writer - POSition ENabled"]
239pub type POSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, BMR_SPEC, bool, O>;
240#[doc = "Field `SPEEDEN` reader - SPEED ENabled"]
241pub type SPEEDEN_R = crate::BitReader<bool>;
242#[doc = "Field `SPEEDEN` writer - SPEED ENabled"]
243pub type SPEEDEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, BMR_SPEC, bool, O>;
244#[doc = "Field `QDTRANS` reader - Quadrature Decoding TRANSparent"]
245pub type QDTRANS_R = crate::BitReader<bool>;
246#[doc = "Field `QDTRANS` writer - Quadrature Decoding TRANSparent"]
247pub type QDTRANS_W<'a, const O: u8> = crate::BitWriter<'a, u32, BMR_SPEC, bool, O>;
248#[doc = "Field `EDGPHA` reader - EDGe on PHA count mode"]
249pub type EDGPHA_R = crate::BitReader<bool>;
250#[doc = "Field `EDGPHA` writer - EDGe on PHA count mode"]
251pub type EDGPHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, BMR_SPEC, bool, O>;
252#[doc = "Field `INVA` reader - INVerted phA"]
253pub type INVA_R = crate::BitReader<bool>;
254#[doc = "Field `INVA` writer - INVerted phA"]
255pub type INVA_W<'a, const O: u8> = crate::BitWriter<'a, u32, BMR_SPEC, bool, O>;
256#[doc = "Field `INVB` reader - INVerted phB"]
257pub type INVB_R = crate::BitReader<bool>;
258#[doc = "Field `INVB` writer - INVerted phB"]
259pub type INVB_W<'a, const O: u8> = crate::BitWriter<'a, u32, BMR_SPEC, bool, O>;
260#[doc = "Field `INVIDX` reader - INVerted InDeX"]
261pub type INVIDX_R = crate::BitReader<bool>;
262#[doc = "Field `INVIDX` writer - INVerted InDeX"]
263pub type INVIDX_W<'a, const O: u8> = crate::BitWriter<'a, u32, BMR_SPEC, bool, O>;
264#[doc = "Field `SWAP` reader - SWAP PHA and PHB"]
265pub type SWAP_R = crate::BitReader<bool>;
266#[doc = "Field `SWAP` writer - SWAP PHA and PHB"]
267pub type SWAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, BMR_SPEC, bool, O>;
268#[doc = "Field `IDXPHB` reader - InDeX pin is PHB pin"]
269pub type IDXPHB_R = crate::BitReader<bool>;
270#[doc = "Field `IDXPHB` writer - InDeX pin is PHB pin"]
271pub type IDXPHB_W<'a, const O: u8> = crate::BitWriter<'a, u32, BMR_SPEC, bool, O>;
272#[doc = "Field `FILTER` reader - "]
273pub type FILTER_R = crate::BitReader<bool>;
274#[doc = "Field `FILTER` writer - "]
275pub type FILTER_W<'a, const O: u8> = crate::BitWriter<'a, u32, BMR_SPEC, bool, O>;
276#[doc = "Field `MAXFILT` reader - MAXimum FILTer"]
277pub type MAXFILT_R = crate::FieldReader<u8, u8>;
278#[doc = "Field `MAXFILT` writer - MAXimum FILTer"]
279pub type MAXFILT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BMR_SPEC, u8, u8, 6, O>;
280impl R {
281 #[doc = "Bits 0:1 - External Clock Signal 0 Selection"]
282 #[inline(always)]
283 pub fn tc0xc0s(&self) -> TC0XC0S_R {
284 TC0XC0S_R::new((self.bits & 3) as u8)
285 }
286 #[doc = "Bits 2:3 - External Clock Signal 1 Selection"]
287 #[inline(always)]
288 pub fn tc1xc1s(&self) -> TC1XC1S_R {
289 TC1XC1S_R::new(((self.bits >> 2) & 3) as u8)
290 }
291 #[doc = "Bits 4:5 - External Clock Signal 2 Selection"]
292 #[inline(always)]
293 pub fn tc2xc2s(&self) -> TC2XC2S_R {
294 TC2XC2S_R::new(((self.bits >> 4) & 3) as u8)
295 }
296 #[doc = "Bit 8 - Quadrature Decoder ENabled"]
297 #[inline(always)]
298 pub fn qden(&self) -> QDEN_R {
299 QDEN_R::new(((self.bits >> 8) & 1) != 0)
300 }
301 #[doc = "Bit 9 - POSition ENabled"]
302 #[inline(always)]
303 pub fn posen(&self) -> POSEN_R {
304 POSEN_R::new(((self.bits >> 9) & 1) != 0)
305 }
306 #[doc = "Bit 10 - SPEED ENabled"]
307 #[inline(always)]
308 pub fn speeden(&self) -> SPEEDEN_R {
309 SPEEDEN_R::new(((self.bits >> 10) & 1) != 0)
310 }
311 #[doc = "Bit 11 - Quadrature Decoding TRANSparent"]
312 #[inline(always)]
313 pub fn qdtrans(&self) -> QDTRANS_R {
314 QDTRANS_R::new(((self.bits >> 11) & 1) != 0)
315 }
316 #[doc = "Bit 12 - EDGe on PHA count mode"]
317 #[inline(always)]
318 pub fn edgpha(&self) -> EDGPHA_R {
319 EDGPHA_R::new(((self.bits >> 12) & 1) != 0)
320 }
321 #[doc = "Bit 13 - INVerted phA"]
322 #[inline(always)]
323 pub fn inva(&self) -> INVA_R {
324 INVA_R::new(((self.bits >> 13) & 1) != 0)
325 }
326 #[doc = "Bit 14 - INVerted phB"]
327 #[inline(always)]
328 pub fn invb(&self) -> INVB_R {
329 INVB_R::new(((self.bits >> 14) & 1) != 0)
330 }
331 #[doc = "Bit 15 - INVerted InDeX"]
332 #[inline(always)]
333 pub fn invidx(&self) -> INVIDX_R {
334 INVIDX_R::new(((self.bits >> 15) & 1) != 0)
335 }
336 #[doc = "Bit 16 - SWAP PHA and PHB"]
337 #[inline(always)]
338 pub fn swap(&self) -> SWAP_R {
339 SWAP_R::new(((self.bits >> 16) & 1) != 0)
340 }
341 #[doc = "Bit 17 - InDeX pin is PHB pin"]
342 #[inline(always)]
343 pub fn idxphb(&self) -> IDXPHB_R {
344 IDXPHB_R::new(((self.bits >> 17) & 1) != 0)
345 }
346 #[doc = "Bit 19"]
347 #[inline(always)]
348 pub fn filter(&self) -> FILTER_R {
349 FILTER_R::new(((self.bits >> 19) & 1) != 0)
350 }
351 #[doc = "Bits 20:25 - MAXimum FILTer"]
352 #[inline(always)]
353 pub fn maxfilt(&self) -> MAXFILT_R {
354 MAXFILT_R::new(((self.bits >> 20) & 0x3f) as u8)
355 }
356}
357impl W {
358 #[doc = "Bits 0:1 - External Clock Signal 0 Selection"]
359 #[inline(always)]
360 #[must_use]
361 pub fn tc0xc0s(&mut self) -> TC0XC0S_W<0> {
362 TC0XC0S_W::new(self)
363 }
364 #[doc = "Bits 2:3 - External Clock Signal 1 Selection"]
365 #[inline(always)]
366 #[must_use]
367 pub fn tc1xc1s(&mut self) -> TC1XC1S_W<2> {
368 TC1XC1S_W::new(self)
369 }
370 #[doc = "Bits 4:5 - External Clock Signal 2 Selection"]
371 #[inline(always)]
372 #[must_use]
373 pub fn tc2xc2s(&mut self) -> TC2XC2S_W<4> {
374 TC2XC2S_W::new(self)
375 }
376 #[doc = "Bit 8 - Quadrature Decoder ENabled"]
377 #[inline(always)]
378 #[must_use]
379 pub fn qden(&mut self) -> QDEN_W<8> {
380 QDEN_W::new(self)
381 }
382 #[doc = "Bit 9 - POSition ENabled"]
383 #[inline(always)]
384 #[must_use]
385 pub fn posen(&mut self) -> POSEN_W<9> {
386 POSEN_W::new(self)
387 }
388 #[doc = "Bit 10 - SPEED ENabled"]
389 #[inline(always)]
390 #[must_use]
391 pub fn speeden(&mut self) -> SPEEDEN_W<10> {
392 SPEEDEN_W::new(self)
393 }
394 #[doc = "Bit 11 - Quadrature Decoding TRANSparent"]
395 #[inline(always)]
396 #[must_use]
397 pub fn qdtrans(&mut self) -> QDTRANS_W<11> {
398 QDTRANS_W::new(self)
399 }
400 #[doc = "Bit 12 - EDGe on PHA count mode"]
401 #[inline(always)]
402 #[must_use]
403 pub fn edgpha(&mut self) -> EDGPHA_W<12> {
404 EDGPHA_W::new(self)
405 }
406 #[doc = "Bit 13 - INVerted phA"]
407 #[inline(always)]
408 #[must_use]
409 pub fn inva(&mut self) -> INVA_W<13> {
410 INVA_W::new(self)
411 }
412 #[doc = "Bit 14 - INVerted phB"]
413 #[inline(always)]
414 #[must_use]
415 pub fn invb(&mut self) -> INVB_W<14> {
416 INVB_W::new(self)
417 }
418 #[doc = "Bit 15 - INVerted InDeX"]
419 #[inline(always)]
420 #[must_use]
421 pub fn invidx(&mut self) -> INVIDX_W<15> {
422 INVIDX_W::new(self)
423 }
424 #[doc = "Bit 16 - SWAP PHA and PHB"]
425 #[inline(always)]
426 #[must_use]
427 pub fn swap(&mut self) -> SWAP_W<16> {
428 SWAP_W::new(self)
429 }
430 #[doc = "Bit 17 - InDeX pin is PHB pin"]
431 #[inline(always)]
432 #[must_use]
433 pub fn idxphb(&mut self) -> IDXPHB_W<17> {
434 IDXPHB_W::new(self)
435 }
436 #[doc = "Bit 19"]
437 #[inline(always)]
438 #[must_use]
439 pub fn filter(&mut self) -> FILTER_W<19> {
440 FILTER_W::new(self)
441 }
442 #[doc = "Bits 20:25 - MAXimum FILTer"]
443 #[inline(always)]
444 #[must_use]
445 pub fn maxfilt(&mut self) -> MAXFILT_W<20> {
446 MAXFILT_W::new(self)
447 }
448 #[doc = "Writes raw bits to the register."]
449 #[inline(always)]
450 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
451 self.0.bits(bits);
452 self
453 }
454}
455#[doc = "Block Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bmr](index.html) module"]
456pub struct BMR_SPEC;
457impl crate::RegisterSpec for BMR_SPEC {
458 type Ux = u32;
459}
460#[doc = "`read()` method returns [bmr::R](R) reader structure"]
461impl crate::Readable for BMR_SPEC {
462 type Reader = R;
463}
464#[doc = "`write(|w| ..)` method takes [bmr::W](W) writer structure"]
465impl crate::Writable for BMR_SPEC {
466 type Writer = W;
467 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
468 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
469}
470#[doc = "`reset()` method sets BMR to value 0"]
471impl crate::Resettable for BMR_SPEC {
472 const RESET_VALUE: Self::Ux = 0;
473}