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#[doc = "Reader of register CFG"] pub type R = crate::R<u32, super::CFG>; #[doc = "Writer for register CFG"] pub type W = crate::W<u32, super::CFG>; #[doc = "Register CFG `reset()`'s with value 0"] impl crate::ResetValue for super::CFG { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `REFSEL`"] pub type REFSEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `REFSEL`"] pub struct REFSEL_W<'a> { w: &'a mut W, } impl<'a> REFSEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 1)) | (((value as u32) & 0x07) << 1); self.w } } #[doc = "Reader of field `SPEED`"] pub type SPEED_R = crate::R<u8, u8>; #[doc = "Write proxy for field `SPEED`"] pub struct SPEED_W<'a> { w: &'a mut W, } impl<'a> SPEED_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4); self.w } } #[doc = "Reader of field `CLKSEL`"] pub type CLKSEL_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CLKSEL`"] pub struct CLKSEL_W<'a> { w: &'a mut W, } impl<'a> CLKSEL_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); self.w } } #[doc = "Reader of field `PRESCAL`"] pub type PRESCAL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `PRESCAL`"] pub struct PRESCAL_W<'a> { w: &'a mut W, } impl<'a> PRESCAL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u32) & 0x07) << 8); self.w } } impl R { #[doc = "Bits 1:3 - ADC Reference Selection"] #[inline(always)] pub fn refsel(&self) -> REFSEL_R { REFSEL_R::new(((self.bits >> 1) & 0x07) as u8) } #[doc = "Bits 4:5 - ADC current reduction"] #[inline(always)] pub fn speed(&self) -> SPEED_R { SPEED_R::new(((self.bits >> 4) & 0x03) as u8) } #[doc = "Bit 6 - Clock Selection for sequencer/ADC cell"] #[inline(always)] pub fn clksel(&self) -> CLKSEL_R { CLKSEL_R::new(((self.bits >> 6) & 0x01) != 0) } #[doc = "Bits 8:10 - Prescaler Rate Selection"] #[inline(always)] pub fn prescal(&self) -> PRESCAL_R { PRESCAL_R::new(((self.bits >> 8) & 0x07) as u8) } } impl W { #[doc = "Bits 1:3 - ADC Reference Selection"] #[inline(always)] pub fn refsel(&mut self) -> REFSEL_W { REFSEL_W { w: self } } #[doc = "Bits 4:5 - ADC current reduction"] #[inline(always)] pub fn speed(&mut self) -> SPEED_W { SPEED_W { w: self } } #[doc = "Bit 6 - Clock Selection for sequencer/ADC cell"] #[inline(always)] pub fn clksel(&mut self) -> CLKSEL_W { CLKSEL_W { w: self } } #[doc = "Bits 8:10 - Prescaler Rate Selection"] #[inline(always)] pub fn prescal(&mut self) -> PRESCAL_W { PRESCAL_W { w: self } } }