Module atsam4ls4c_pac::twis0 [−][src]
Two-wire Slave Interface 0
Modules
cr | Control Register |
hssrr | HS-mode Slew Rate Register |
hstr | HS-mode Timing Register |
idr | Interrupt Disable Register |
ier | Interrupt Enable Register |
imr | Interrupt Mask Register |
nbytes | NBYTES Register |
pecr | Packet Error Check Register |
pr | Parameter Register |
rhr | Receive Holding Register |
scr | Status Clear Register |
sr | Status Register |
srr | Slew Rate Register |
thr | Transmit Holding Register |
tr | Timing Register |
vr | Version Register |
Structs
RegisterBlock | Register block |
Type Definitions
CR | Control Register |
HSSRR | HS-mode Slew Rate Register |
HSTR | HS-mode Timing Register |
IDR | Interrupt Disable Register |
IER | Interrupt Enable Register |
IMR | Interrupt Mask Register |
NBYTES | NBYTES Register |
PECR | Packet Error Check Register |
PR | Parameter Register |
RHR | Receive Holding Register |
SCR | Status Clear Register |
SR | Status Register |
SRR | Slew Rate Register |
THR | Transmit Holding Register |
TR | Timing Register |
VR | Version Register |