Struct atsam4lc8c::gpio::RegisterBlock
[−]
[src]
#[repr(C)]pub struct RegisterBlock { pub gper0: GPER, pub gpers0: GPERS, pub gperc0: GPERC, pub gpert0: GPERT, pub pmr00: PMR0, pub pmr0s0: PMR0S, pub pmr0c0: PMR0C, pub pmr0t0: PMR0T, pub pmr10: PMR1, pub pmr1s0: PMR1S, pub pmr1c0: PMR1C, pub pmr1t0: PMR1T, pub pmr20: PMR2, pub pmr2s0: PMR2S, pub pmr2c0: PMR2C, pub pmr2t0: PMR2T, pub oder0: ODER, pub oders0: ODERS, pub oderc0: ODERC, pub odert0: ODERT, pub ovr0: OVR, pub ovrs0: OVRS, pub ovrc0: OVRC, pub ovrt0: OVRT, pub pvr0: PVR, pub puer0: PUER, pub puers0: PUERS, pub puerc0: PUERC, pub puert0: PUERT, pub pder0: PDER, pub pders0: PDERS, pub pderc0: PDERC, pub pdert0: PDERT, pub ier0: IER, pub iers0: IERS, pub ierc0: IERC, pub iert0: IERT, pub imr00: IMR0, pub imr0s0: IMR0S, pub imr0c0: IMR0C, pub imr0t0: IMR0T, pub imr10: IMR1, pub imr1s0: IMR1S, pub imr1c0: IMR1C, pub imr1t0: IMR1T, pub gfer0: GFER, pub gfers0: GFERS, pub gferc0: GFERC, pub gfert0: GFERT, pub ifr0: IFR, pub ifrc0: IFRC, pub odmer0: ODMER, pub odmers0: ODMERS, pub odmerc0: ODMERC, pub odmert0: ODMERT, pub odcr00: ODCR0, pub odcr0s0: ODCR0S, pub odcr0c0: ODCR0C, pub odcr0t0: ODCR0T, pub odcr10: ODCR1, pub odcr1s0: ODCR1S, pub odcr1c0: ODCR1C, pub odcr1t0: ODCR1T, pub osrr00: OSRR0, pub osrr0s0: OSRR0S, pub osrr0c0: OSRR0C, pub osrr0t0: OSRR0T, pub ster0: STER, pub sters0: STERS, pub sterc0: STERC, pub stert0: STERT, pub ever0: EVER, pub evers0: EVERS, pub everc0: EVERC, pub evert0: EVERT, pub lock0: LOCK, pub locks0: LOCKS, pub lockc0: LOCKC, pub lockt0: LOCKT, pub unlock0: UNLOCK, pub asr0: ASR, pub parameter0: PARAMETER, pub version0: VERSION, pub gper1: GPER, pub gpers1: GPERS, pub gperc1: GPERC, pub gpert1: GPERT, pub pmr01: PMR0, pub pmr0s1: PMR0S, pub pmr0c1: PMR0C, pub pmr0t1: PMR0T, pub pmr11: PMR1, pub pmr1s1: PMR1S, pub pmr1c1: PMR1C, pub pmr1t1: PMR1T, pub pmr21: PMR2, pub pmr2s1: PMR2S, pub pmr2c1: PMR2C, pub pmr2t1: PMR2T, pub oder1: ODER, pub oders1: ODERS, pub oderc1: ODERC, pub odert1: ODERT, pub ovr1: OVR, pub ovrs1: OVRS, pub ovrc1: OVRC, pub ovrt1: OVRT, pub pvr1: PVR, pub puer1: PUER, pub puers1: PUERS, pub puerc1: PUERC, pub puert1: PUERT, pub pder1: PDER, pub pders1: PDERS, pub pderc1: PDERC, pub pdert1: PDERT, pub ier1: IER, pub iers1: IERS, pub ierc1: IERC, pub iert1: IERT, pub imr01: IMR0, pub imr0s1: IMR0S, pub imr0c1: IMR0C, pub imr0t1: IMR0T, pub imr11: IMR1, pub imr1s1: IMR1S, pub imr1c1: IMR1C, pub imr1t1: IMR1T, pub gfer1: GFER, pub gfers1: GFERS, pub gferc1: GFERC, pub gfert1: GFERT, pub ifr1: IFR, pub ifrc1: IFRC, pub odmer1: ODMER, pub odmers1: ODMERS, pub odmerc1: ODMERC, pub odmert1: ODMERT, pub odcr01: ODCR0, pub odcr0s1: ODCR0S, pub odcr0c1: ODCR0C, pub odcr0t1: ODCR0T, pub odcr11: ODCR1, pub odcr1s1: ODCR1S, pub odcr1c1: ODCR1C, pub odcr1t1: ODCR1T, pub osrr01: OSRR0, pub osrr0s1: OSRR0S, pub osrr0c1: OSRR0C, pub osrr0t1: OSRR0T, pub ster1: STER, pub sters1: STERS, pub sterc1: STERC, pub stert1: STERT, pub ever1: EVER, pub evers1: EVERS, pub everc1: EVERC, pub evert1: EVERT, pub lock1: LOCK, pub locks1: LOCKS, pub lockc1: LOCKC, pub lockt1: LOCKT, pub unlock1: UNLOCK, pub asr1: ASR, pub parameter1: PARAMETER, pub version1: VERSION, pub gper2: GPER, pub gpers2: GPERS, pub gperc2: GPERC, pub gpert2: GPERT, pub pmr02: PMR0, pub pmr0s2: PMR0S, pub pmr0c2: PMR0C, pub pmr0t2: PMR0T, pub pmr12: PMR1, pub pmr1s2: PMR1S, pub pmr1c2: PMR1C, pub pmr1t2: PMR1T, pub pmr22: PMR2, pub pmr2s2: PMR2S, pub pmr2c2: PMR2C, pub pmr2t2: PMR2T, pub oder2: ODER, pub oders2: ODERS, pub oderc2: ODERC, pub odert2: ODERT, pub ovr2: OVR, pub ovrs2: OVRS, pub ovrc2: OVRC, pub ovrt2: OVRT, pub pvr2: PVR, pub puer2: PUER, pub puers2: PUERS, pub puerc2: PUERC, pub puert2: PUERT, pub pder2: PDER, pub pders2: PDERS, pub pderc2: PDERC, pub pdert2: PDERT, pub ier2: IER, pub iers2: IERS, pub ierc2: IERC, pub iert2: IERT, pub imr02: IMR0, pub imr0s2: IMR0S, pub imr0c2: IMR0C, pub imr0t2: IMR0T, pub imr12: IMR1, pub imr1s2: IMR1S, pub imr1c2: IMR1C, pub imr1t2: IMR1T, pub gfer2: GFER, pub gfers2: GFERS, pub gferc2: GFERC, pub gfert2: GFERT, pub ifr2: IFR, pub ifrc2: IFRC, pub odmer2: ODMER, pub odmers2: ODMERS, pub odmerc2: ODMERC, pub odmert2: ODMERT, pub odcr02: ODCR0, pub odcr0s2: ODCR0S, pub odcr0c2: ODCR0C, pub odcr0t2: ODCR0T, pub odcr12: ODCR1, pub odcr1s2: ODCR1S, pub odcr1c2: ODCR1C, pub odcr1t2: ODCR1T, pub osrr02: OSRR0, pub osrr0s2: OSRR0S, pub osrr0c2: OSRR0C, pub osrr0t2: OSRR0T, pub ster2: STER, pub sters2: STERS, pub sterc2: STERC, pub stert2: STERT, pub ever2: EVER, pub evers2: EVERS, pub everc2: EVERC, pub evert2: EVERT, pub lock2: LOCK, pub locks2: LOCKS, pub lockc2: LOCKC, pub lockt2: LOCKT, pub unlock2: UNLOCK, pub asr2: ASR, pub parameter2: PARAMETER, pub version2: VERSION, // some fields omitted }
Register block
Fields
gper0: GPER
0x00 - GPIO Enable Register
gpers0: GPERS
0x04 - GPIO Enable Register - Set
gperc0: GPERC
0x08 - GPIO Enable Register - Clear
gpert0: GPERT
0x0c - GPIO Enable Register - Toggle
pmr00: PMR0
0x10 - Peripheral Mux Register 0
pmr0s0: PMR0S
0x14 - Peripheral Mux Register 0 - Set
pmr0c0: PMR0C
0x18 - Peripheral Mux Register 0 - Clear
pmr0t0: PMR0T
0x1c - Peripheral Mux Register 0 - Toggle
pmr10: PMR1
0x20 - Peripheral Mux Register 1
pmr1s0: PMR1S
0x24 - Peripheral Mux Register 1 - Set
pmr1c0: PMR1C
0x28 - Peripheral Mux Register 1 - Clear
pmr1t0: PMR1T
0x2c - Peripheral Mux Register 1 - Toggle
pmr20: PMR2
0x30 - Peripheral Mux Register 2
pmr2s0: PMR2S
0x34 - Peripheral Mux Register 2 - Set
pmr2c0: PMR2C
0x38 - Peripheral Mux Register 2 - Clear
pmr2t0: PMR2T
0x3c - Peripheral Mux Register 2 - Toggle
oder0: ODER
0x40 - Output Driver Enable Register
oders0: ODERS
0x44 - Output Driver Enable Register - Set
oderc0: ODERC
0x48 - Output Driver Enable Register - Clear
odert0: ODERT
0x4c - Output Driver Enable Register - Toggle
ovr0: OVR
0x50 - Output Value Register
ovrs0: OVRS
0x54 - Output Value Register - Set
ovrc0: OVRC
0x58 - Output Value Register - Clear
ovrt0: OVRT
0x5c - Output Value Register - Toggle
pvr0: PVR
0x60 - Pin Value Register
puer0: PUER
0x70 - Pull-up Enable Register
puers0: PUERS
0x74 - Pull-up Enable Register - Set
puerc0: PUERC
0x78 - Pull-up Enable Register - Clear
puert0: PUERT
0x7c - Pull-up Enable Register - Toggle
pder0: PDER
0x80 - Pull-down Enable Register
pders0: PDERS
0x84 - Pull-down Enable Register - Set
pderc0: PDERC
0x88 - Pull-down Enable Register - Clear
pdert0: PDERT
0x8c - Pull-down Enable Register - Toggle
ier0: IER
0x90 - Interrupt Enable Register
iers0: IERS
0x94 - Interrupt Enable Register - Set
ierc0: IERC
0x98 - Interrupt Enable Register - Clear
iert0: IERT
0x9c - Interrupt Enable Register - Toggle
imr00: IMR0
0xa0 - Interrupt Mode Register 0
imr0s0: IMR0S
0xa4 - Interrupt Mode Register 0 - Set
imr0c0: IMR0C
0xa8 - Interrupt Mode Register 0 - Clear
imr0t0: IMR0T
0xac - Interrupt Mode Register 0 - Toggle
imr10: IMR1
0xb0 - Interrupt Mode Register 1
imr1s0: IMR1S
0xb4 - Interrupt Mode Register 1 - Set
imr1c0: IMR1C
0xb8 - Interrupt Mode Register 1 - Clear
imr1t0: IMR1T
0xbc - Interrupt Mode Register 1 - Toggle
gfer0: GFER
0xc0 - Glitch Filter Enable Register
gfers0: GFERS
0xc4 - Glitch Filter Enable Register - Set
gferc0: GFERC
0xc8 - Glitch Filter Enable Register - Clear
gfert0: GFERT
0xcc - Glitch Filter Enable Register - Toggle
ifr0: IFR
0xd0 - Interrupt Flag Register
ifrc0: IFRC
0xd8 - Interrupt Flag Register - Clear
odmer0: ODMER
0xe0 - Open Drain Mode Register
odmers0: ODMERS
0xe4 - Open Drain Mode Register - Set
odmerc0: ODMERC
0xe8 - Open Drain Mode Register - Clear
odmert0: ODMERT
0xec - Open Drain Mode Register - Toggle
odcr00: ODCR0
0x100 - Output Driving Capability Register 0
odcr0s0: ODCR0S
0x104 - Output Driving Capability Register 0 - Set
odcr0c0: ODCR0C
0x108 - Output Driving Capability Register 0 - Clear
odcr0t0: ODCR0T
0x10c - Output Driving Capability Register 0 - Toggle
odcr10: ODCR1
0x110 - Output Driving Capability Register 1
odcr1s0: ODCR1S
0x114 - Output Driving Capability Register 1 - Set
odcr1c0: ODCR1C
0x118 - Output Driving Capability Register 1 - Clear
odcr1t0: ODCR1T
0x11c - Output Driving Capability Register 1 - Toggle
osrr00: OSRR0
0x130 - Output Slew Rate Register 0
osrr0s0: OSRR0S
0x134 - Output Slew Rate Register 0 - Set
osrr0c0: OSRR0C
0x138 - Output Slew Rate Register 0 - Clear
osrr0t0: OSRR0T
0x13c - Output Slew Rate Register 0 - Toggle
ster0: STER
0x160 - Schmitt Trigger Enable Register
sters0: STERS
0x164 - Schmitt Trigger Enable Register - Set
sterc0: STERC
0x168 - Schmitt Trigger Enable Register - Clear
stert0: STERT
0x16c - Schmitt Trigger Enable Register - Toggle
ever0: EVER
0x180 - Event Enable Register
evers0: EVERS
0x184 - Event Enable Register - Set
everc0: EVERC
0x188 - Event Enable Register - Clear
evert0: EVERT
0x18c - Event Enable Register - Toggle
lock0: LOCK
0x1a0 - Lock Register
locks0: LOCKS
0x1a4 - Lock Register - Set
lockc0: LOCKC
0x1a8 - Lock Register - Clear
lockt0: LOCKT
0x1ac - Lock Register - Toggle
unlock0: UNLOCK
0x1e0 - Unlock Register
asr0: ASR
0x1e4 - Access Status Register
parameter0: PARAMETER
0x1f8 - Parameter Register
version0: VERSION
0x1fc - Version Register
gper1: GPER
0x200 - GPIO Enable Register
gpers1: GPERS
0x204 - GPIO Enable Register - Set
gperc1: GPERC
0x208 - GPIO Enable Register - Clear
gpert1: GPERT
0x20c - GPIO Enable Register - Toggle
pmr01: PMR0
0x210 - Peripheral Mux Register 0
pmr0s1: PMR0S
0x214 - Peripheral Mux Register 0 - Set
pmr0c1: PMR0C
0x218 - Peripheral Mux Register 0 - Clear
pmr0t1: PMR0T
0x21c - Peripheral Mux Register 0 - Toggle
pmr11: PMR1
0x220 - Peripheral Mux Register 1
pmr1s1: PMR1S
0x224 - Peripheral Mux Register 1 - Set
pmr1c1: PMR1C
0x228 - Peripheral Mux Register 1 - Clear
pmr1t1: PMR1T
0x22c - Peripheral Mux Register 1 - Toggle
pmr21: PMR2
0x230 - Peripheral Mux Register 2
pmr2s1: PMR2S
0x234 - Peripheral Mux Register 2 - Set
pmr2c1: PMR2C
0x238 - Peripheral Mux Register 2 - Clear
pmr2t1: PMR2T
0x23c - Peripheral Mux Register 2 - Toggle
oder1: ODER
0x240 - Output Driver Enable Register
oders1: ODERS
0x244 - Output Driver Enable Register - Set
oderc1: ODERC
0x248 - Output Driver Enable Register - Clear
odert1: ODERT
0x24c - Output Driver Enable Register - Toggle
ovr1: OVR
0x250 - Output Value Register
ovrs1: OVRS
0x254 - Output Value Register - Set
ovrc1: OVRC
0x258 - Output Value Register - Clear
ovrt1: OVRT
0x25c - Output Value Register - Toggle
pvr1: PVR
0x260 - Pin Value Register
puer1: PUER
0x270 - Pull-up Enable Register
puers1: PUERS
0x274 - Pull-up Enable Register - Set
puerc1: PUERC
0x278 - Pull-up Enable Register - Clear
puert1: PUERT
0x27c - Pull-up Enable Register - Toggle
pder1: PDER
0x280 - Pull-down Enable Register
pders1: PDERS
0x284 - Pull-down Enable Register - Set
pderc1: PDERC
0x288 - Pull-down Enable Register - Clear
pdert1: PDERT
0x28c - Pull-down Enable Register - Toggle
ier1: IER
0x290 - Interrupt Enable Register
iers1: IERS
0x294 - Interrupt Enable Register - Set
ierc1: IERC
0x298 - Interrupt Enable Register - Clear
iert1: IERT
0x29c - Interrupt Enable Register - Toggle
imr01: IMR0
0x2a0 - Interrupt Mode Register 0
imr0s1: IMR0S
0x2a4 - Interrupt Mode Register 0 - Set
imr0c1: IMR0C
0x2a8 - Interrupt Mode Register 0 - Clear
imr0t1: IMR0T
0x2ac - Interrupt Mode Register 0 - Toggle
imr11: IMR1
0x2b0 - Interrupt Mode Register 1
imr1s1: IMR1S
0x2b4 - Interrupt Mode Register 1 - Set
imr1c1: IMR1C
0x2b8 - Interrupt Mode Register 1 - Clear
imr1t1: IMR1T
0x2bc - Interrupt Mode Register 1 - Toggle
gfer1: GFER
0x2c0 - Glitch Filter Enable Register
gfers1: GFERS
0x2c4 - Glitch Filter Enable Register - Set
gferc1: GFERC
0x2c8 - Glitch Filter Enable Register - Clear
gfert1: GFERT
0x2cc - Glitch Filter Enable Register - Toggle
ifr1: IFR
0x2d0 - Interrupt Flag Register
ifrc1: IFRC
0x2d8 - Interrupt Flag Register - Clear
odmer1: ODMER
0x2e0 - Open Drain Mode Register
odmers1: ODMERS
0x2e4 - Open Drain Mode Register - Set
odmerc1: ODMERC
0x2e8 - Open Drain Mode Register - Clear
odmert1: ODMERT
0x2ec - Open Drain Mode Register - Toggle
odcr01: ODCR0
0x300 - Output Driving Capability Register 0
odcr0s1: ODCR0S
0x304 - Output Driving Capability Register 0 - Set
odcr0c1: ODCR0C
0x308 - Output Driving Capability Register 0 - Clear
odcr0t1: ODCR0T
0x30c - Output Driving Capability Register 0 - Toggle
odcr11: ODCR1
0x310 - Output Driving Capability Register 1
odcr1s1: ODCR1S
0x314 - Output Driving Capability Register 1 - Set
odcr1c1: ODCR1C
0x318 - Output Driving Capability Register 1 - Clear
odcr1t1: ODCR1T
0x31c - Output Driving Capability Register 1 - Toggle
osrr01: OSRR0
0x330 - Output Slew Rate Register 0
osrr0s1: OSRR0S
0x334 - Output Slew Rate Register 0 - Set
osrr0c1: OSRR0C
0x338 - Output Slew Rate Register 0 - Clear
osrr0t1: OSRR0T
0x33c - Output Slew Rate Register 0 - Toggle
ster1: STER
0x360 - Schmitt Trigger Enable Register
sters1: STERS
0x364 - Schmitt Trigger Enable Register - Set
sterc1: STERC
0x368 - Schmitt Trigger Enable Register - Clear
stert1: STERT
0x36c - Schmitt Trigger Enable Register - Toggle
ever1: EVER
0x380 - Event Enable Register
evers1: EVERS
0x384 - Event Enable Register - Set
everc1: EVERC
0x388 - Event Enable Register - Clear
evert1: EVERT
0x38c - Event Enable Register - Toggle
lock1: LOCK
0x3a0 - Lock Register
locks1: LOCKS
0x3a4 - Lock Register - Set
lockc1: LOCKC
0x3a8 - Lock Register - Clear
lockt1: LOCKT
0x3ac - Lock Register - Toggle
unlock1: UNLOCK
0x3e0 - Unlock Register
asr1: ASR
0x3e4 - Access Status Register
parameter1: PARAMETER
0x3f8 - Parameter Register
version1: VERSION
0x3fc - Version Register
gper2: GPER
0x400 - GPIO Enable Register
gpers2: GPERS
0x404 - GPIO Enable Register - Set
gperc2: GPERC
0x408 - GPIO Enable Register - Clear
gpert2: GPERT
0x40c - GPIO Enable Register - Toggle
pmr02: PMR0
0x410 - Peripheral Mux Register 0
pmr0s2: PMR0S
0x414 - Peripheral Mux Register 0 - Set
pmr0c2: PMR0C
0x418 - Peripheral Mux Register 0 - Clear
pmr0t2: PMR0T
0x41c - Peripheral Mux Register 0 - Toggle
pmr12: PMR1
0x420 - Peripheral Mux Register 1
pmr1s2: PMR1S
0x424 - Peripheral Mux Register 1 - Set
pmr1c2: PMR1C
0x428 - Peripheral Mux Register 1 - Clear
pmr1t2: PMR1T
0x42c - Peripheral Mux Register 1 - Toggle
pmr22: PMR2
0x430 - Peripheral Mux Register 2
pmr2s2: PMR2S
0x434 - Peripheral Mux Register 2 - Set
pmr2c2: PMR2C
0x438 - Peripheral Mux Register 2 - Clear
pmr2t2: PMR2T
0x43c - Peripheral Mux Register 2 - Toggle
oder2: ODER
0x440 - Output Driver Enable Register
oders2: ODERS
0x444 - Output Driver Enable Register - Set
oderc2: ODERC
0x448 - Output Driver Enable Register - Clear
odert2: ODERT
0x44c - Output Driver Enable Register - Toggle
ovr2: OVR
0x450 - Output Value Register
ovrs2: OVRS
0x454 - Output Value Register - Set
ovrc2: OVRC
0x458 - Output Value Register - Clear
ovrt2: OVRT
0x45c - Output Value Register - Toggle
pvr2: PVR
0x460 - Pin Value Register
puer2: PUER
0x470 - Pull-up Enable Register
puers2: PUERS
0x474 - Pull-up Enable Register - Set
puerc2: PUERC
0x478 - Pull-up Enable Register - Clear
puert2: PUERT
0x47c - Pull-up Enable Register - Toggle
pder2: PDER
0x480 - Pull-down Enable Register
pders2: PDERS
0x484 - Pull-down Enable Register - Set
pderc2: PDERC
0x488 - Pull-down Enable Register - Clear
pdert2: PDERT
0x48c - Pull-down Enable Register - Toggle
ier2: IER
0x490 - Interrupt Enable Register
iers2: IERS
0x494 - Interrupt Enable Register - Set
ierc2: IERC
0x498 - Interrupt Enable Register - Clear
iert2: IERT
0x49c - Interrupt Enable Register - Toggle
imr02: IMR0
0x4a0 - Interrupt Mode Register 0
imr0s2: IMR0S
0x4a4 - Interrupt Mode Register 0 - Set
imr0c2: IMR0C
0x4a8 - Interrupt Mode Register 0 - Clear
imr0t2: IMR0T
0x4ac - Interrupt Mode Register 0 - Toggle
imr12: IMR1
0x4b0 - Interrupt Mode Register 1
imr1s2: IMR1S
0x4b4 - Interrupt Mode Register 1 - Set
imr1c2: IMR1C
0x4b8 - Interrupt Mode Register 1 - Clear
imr1t2: IMR1T
0x4bc - Interrupt Mode Register 1 - Toggle
gfer2: GFER
0x4c0 - Glitch Filter Enable Register
gfers2: GFERS
0x4c4 - Glitch Filter Enable Register - Set
gferc2: GFERC
0x4c8 - Glitch Filter Enable Register - Clear
gfert2: GFERT
0x4cc - Glitch Filter Enable Register - Toggle
ifr2: IFR
0x4d0 - Interrupt Flag Register
ifrc2: IFRC
0x4d8 - Interrupt Flag Register - Clear
odmer2: ODMER
0x4e0 - Open Drain Mode Register
odmers2: ODMERS
0x4e4 - Open Drain Mode Register - Set
odmerc2: ODMERC
0x4e8 - Open Drain Mode Register - Clear
odmert2: ODMERT
0x4ec - Open Drain Mode Register - Toggle
odcr02: ODCR0
0x500 - Output Driving Capability Register 0
odcr0s2: ODCR0S
0x504 - Output Driving Capability Register 0 - Set
odcr0c2: ODCR0C
0x508 - Output Driving Capability Register 0 - Clear
odcr0t2: ODCR0T
0x50c - Output Driving Capability Register 0 - Toggle
odcr12: ODCR1
0x510 - Output Driving Capability Register 1
odcr1s2: ODCR1S
0x514 - Output Driving Capability Register 1 - Set
odcr1c2: ODCR1C
0x518 - Output Driving Capability Register 1 - Clear
odcr1t2: ODCR1T
0x51c - Output Driving Capability Register 1 - Toggle
osrr02: OSRR0
0x530 - Output Slew Rate Register 0
osrr0s2: OSRR0S
0x534 - Output Slew Rate Register 0 - Set
osrr0c2: OSRR0C
0x538 - Output Slew Rate Register 0 - Clear
osrr0t2: OSRR0T
0x53c - Output Slew Rate Register 0 - Toggle
ster2: STER
0x560 - Schmitt Trigger Enable Register
sters2: STERS
0x564 - Schmitt Trigger Enable Register - Set
sterc2: STERC
0x568 - Schmitt Trigger Enable Register - Clear
stert2: STERT
0x56c - Schmitt Trigger Enable Register - Toggle
ever2: EVER
0x580 - Event Enable Register
evers2: EVERS
0x584 - Event Enable Register - Set
everc2: EVERC
0x588 - Event Enable Register - Clear
evert2: EVERT
0x58c - Event Enable Register - Toggle
lock2: LOCK
0x5a0 - Lock Register
locks2: LOCKS
0x5a4 - Lock Register - Set
lockc2: LOCKC
0x5a8 - Lock Register - Clear
lockt2: LOCKT
0x5ac - Lock Register - Toggle
unlock2: UNLOCK
0x5e0 - Unlock Register
asr2: ASR
0x5e4 - Access Status Register
parameter2: PARAMETER
0x5f8 - Parameter Register
version2: VERSION
0x5fc - Version Register